Ready

Abstract

In this work, we propose a framework called REconfigurable Accelerator DeploY (READY), the first framework to support polynomial runtime mapping of dataflow applications in high-performance CPU-FPGA platforms. READY introduces an efficient mapping with fine-grained multithreading onto an overlay architecture that hides the latency of a global interconnection network. In addition to our overlay architecture, we show how this system helps solve some of the challenges for FPGA cloud computing adoption in high-performance computing. The framework encapsulates dataflow descriptions by using a target independent, high-level API, and a dataflow model that allows for explicit spatial and temporal parallelism. READY directly maps the dataflow kernels onto the accelerator. Our tool is flexible and extensible and provides the infrastructure to explore different accelerator designs. We validate READY on the Intel Harp platform, and our experimental results show an average 2x execution runtime improvement when compared to an 8-thread multi-core processor.

Fast flow cloud: A stream dataflow framework for cloud FPGA accelerator overlays at runtime

“…We have validated our previous work 9,10 in an HARPv2 academic environment. We propose extending these earlier works by targeting AWS F1 reconfigurable hardware-based accelerators, AWS provides a better infrastructure to developers and high-level users, while HARPv2 focuses on research.…”

“…Nevertheless, all modules should be defined at design time and should be compatible in size to fit the pre-allocated reserved reconfigurable area. An overlay [7][8][9] is a second option that mitigates the FPGA placement and routing time. Li et al 7,8 propose a time-multiplexed CGRA overlay.…”

“…Finally, the READY 9 and FFC tool combines advantages of previous approaches with a fast mapping and reconfiguration in few milliseconds.…”

“…Section 6 shows the improvements in the mapping time, reconfiguration time, and performance achieved by FFC in comparison to other overlay-based tools. [6][7][8][9]11 Section 7 discusses related work on FPGA accelerator frameworks. Finally, Section 8 discusses the main conclusions and future work.…”

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

“…The FPCA loop-accelerator described earlier was also prototyped on FPGAs. The READY [176] architecture extends the linear array concept further by also having multiple threads running on the overlay.…”