2022
DOI: 10.1088/1748-0221/17/04/c04023
|View full text |Cite
|
Sign up to set email alerts
|

Readout electronics for the CMS Phase II Endcap Calorimeter: system overview and prototyping experience

Abstract: The frontend readout system for the silicon section of the CMS Phase II Endcap Calorimeter faces unique challenges due to the high channel count and associated bandwidth, limited physical space, as well as radiation tolerance requirements. I will give an overview of the frontend electronics design and will discuss the recent experience obtained from the first test system that integrates the HGCROC2 readout ASIC, lpGBT, and VTRX+ in a realistic manner, linking together prototypes of the hexaboard, engine, and w… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
5
0

Year Published

2022
2022
2024
2024

Publication Types

Select...
4

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(5 citation statements)
references
References 5 publications
0
5
0
Order By: Relevance
“…The third version of the LD Hexaboard, V3-LD-HB (see figure 3(c)), was produced with HGCROC-V3 inside a new LD package (BGA with 0.8 mm pitch) [5] using the optimized stack-up-II. This is close to the on-cassette version, including stepped-holes and mechanical constraints, interface connectors, and mechanical mount points required by other on-cassette PCBs used for the powering and data acquisition [3]. A passage for service routing through the cassettes is also required, further constraining component placement.…”
Section: Low Density Hexaboard Prototypingmentioning
confidence: 89%
“…The third version of the LD Hexaboard, V3-LD-HB (see figure 3(c)), was produced with HGCROC-V3 inside a new LD package (BGA with 0.8 mm pitch) [5] using the optimized stack-up-II. This is close to the on-cassette version, including stepped-holes and mechanical constraints, interface connectors, and mechanical mount points required by other on-cassette PCBs used for the powering and data acquisition [3]. A passage for service routing through the cassettes is also required, further constraining component placement.…”
Section: Low Density Hexaboard Prototypingmentioning
confidence: 89%
“…The trigger path begins on-detector, implemented within two types of ASICS, the HGCROC and the ECON-T, in the front-end electronics (FE) [3].…”
Section: Front-end Electronicsmentioning
confidence: 99%
“…As Super-Trigger-Cell applies no threshold or selection, this is unneeded in this case. The resulting data are forwarded to the back-end electronics via low power GigaBit Transceiver (lpGBT) links at a rate of approximately 10 Gbps [3,5].…”
Section: The Econ-tmentioning
confidence: 99%
“…However, time information cannot be exploited in the trigger path due to bandwidth constraints. The TC data is then sent to the on-detector ECON-T chip via 1.28 Gbit s −1 e-links (see, for instance, [7]). Each ECON-T processes data coming from a single module (3 or 6 HGCROCs).…”
Section: The Dataflow Of Hgcal Trigger Primitivesmentioning
confidence: 99%