Re-encoding for low power state assignment of FSMs

Veeramachaneni, Vamshi; Tyagi, Akhilesh K.; Rajgopal, Suresh

doi:10.1145/224081.224112

Cited by 11 publications

(14 citation statements)

References 12 publications

(12 reference statements)

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“…Hachtel et al recursively used weighted matching and min-cut bi-partitioning methods to re-assign codes [8]. Veeramachaneni et al proposed to perform code exchange locally to improve the coding scheme's power efficiency [31]. Our FSM re-engineering approach is conceptually different from re-encoding in that we do not only re-assign codes to the existing states, but also change the topology of the FSM.…”

Section: B State Encoding For Low Powermentioning

confidence: 99%

See 1 more Smart Citation

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

Lin

Villa

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We propose Finite State Machine (FSM) re-engineering, a performance enhancement framework for FSM synthesis and optimization. It starts with the traditional FSM synthesis procedure, then proceeds to re-construct a functionally equivalent but topologically different FSM based on the optimization objective, and concludes with another round of FSM synthesis on the re-constructed FSM. This approach explores a larger solution space that consists of a set of FSMs functionally equivalent to the original one, making it possible to obtain better solutions than in the original FSM. Guided by the result from the first round of synthesis, the solution space exploration process can be rapid and cost-efficient.We apply this framework to FSM state encoding for power minimization and area minimization. The FSM is first minimized and encoded using existing state encoding algorithms. Then we develop both a heuristic algorithm and a genetic algorithm to re-construct the FSM. Finally, the FSM is reencoded by the same encoding algorithms. To demonstrate the effectiveness of this framework, we conduct experiments on MCNC91 sequential circuit benchmarks. The circuits are read in and synthesized in SIS environment. After FSM re-engineering are performed, we measure the power, area and delay in the newly synthesized circuits. In the powerdriven synthesis, we observe an average 5.5% of total power reduction with 1.3% area increase and 1.3% delay increase. This results are in general better than other low power state encoding techniques on comparable cases. In the area-driven synthesis, we observe an average 2.7% area reduction, 1.8% delay reduction, and 0.4% power increase. Finally, we use integer linear programming to obtain the optimal low power state encoding for benchmarks of small size. We find that the optimal solutions in the re-engineered FSMs are 1% to 8% better than the optimal solutions in the original FSMs in terms of power minimization.

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Section: B State Encoding For Low Powermentioning

confidence: 99%

“…This problem is known to be NP-hard and many heuristic algorithms have been proposed. Such techniques include state encoding with minimal code length [3], [26], [30], nonminimal code length [19], [24] and variable code length [28], state re-encoding approaches [8], [31], and simultaneous power and area optimization encoding [17], [25].…”

Section: Introductionmentioning

confidence: 99%

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

Lin

Villa

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…This effect can be taken into account by defining a steady state probability P(s) for the FSM to be in a given state s [MDLT94] [VTRa95]. This probability is dependent on the state…”

Section: Ise@yel=counti(se[i]#ye[i])mentioning

confidence: 99%

Guaranteeing testability in re-encoding for low power

Chiusano

Corno²,

Prinetto³

et al.

Proceedings Sixth Asian Test Symposium (ATS'97)

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This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimization algorithm is proposed, which is able to explore the trade-off between them. The algorithm is based on a newly proposed power estimation function, and on an estimate of the expected test length of a pseudo-random test session. Given these estimates, a Genetic Algorithm, exploiting some symbolic computations with BDDs, provides a state reencoding for the circuit. The algorithm is expenmentally shown both to provide good results from the power optimization point of view, and to be able to sacrifice, on the designer's request, some of the power and area optimization in favor of testability improvement.

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“…Hachtel et al recursively use weighted matching and mincut bi-partitioning methods to re-assign codes [2]. Veeramachaneni et al propose to perform code exchange locally to improve the coding scheme's power efficiency [9]. Our FSM re-engineering approach is conceptually different from re-encoding in that we look to change the topology of the FSM, not only re-assign codes to the existing states.…”

Section: Related Workmentioning

confidence: 99%

“…This problem is NP-hard and many heuristic algorithms have been proposed mainly based on the idea of assigning codes with small Hamming distance to pairs of states that have a high transition probability. Such techniques include state encoding with minimal code length [1,6,8] and non-minimal code length [3,4]; state re-encoding approaches [2,9]; and techniques that try to minimize power and area simultaneously [5].…”

Section: Introductionmentioning

confidence: 99%

FSM re-engineering and its application in low power state encoding

Lin¹,

Qu²,

Villa³

et al.

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

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We propose Finite State Machine (FSM) re-engineering, a performance enhancement framework for FSM synthesis and optimization procedure. We start with any traditional FSM synthesis and optimization procedure; then re-construct a functionally equivalent but topologically different FSM based on the optimization objective; and conclude with another round of FSM synthesis and optimization (can be the same procedure) on the newly constructed FSM. This allows us to explore a larger solution space that includes synthesis solutions to the functionally equivalent FSMs instead of only the original FSM, making it possible to obtain solutions better than the optimal ones for the original FSM. Guided by the result of the first round FSM synthesis, the solution space exploration process can be rapid and cost-efficient.To demonstrate this framework, we develop a genetic algorithm and a fast heuristic to re-engineer a low power state encoding procedure POW3 [1]. On average, POW3 can reduce the switching activity by 12% over non-power-driven state encoding schemes on the MCNC FSM benchmarks. We then re-engineer these benchmarks by the proposed genetic algorithm and heuristic respectively. When we apply POW3 to the re-engineered FSMs, we observe an additional 8.9% and 6.0% switching activity reduction. This translates to an average of 7.9% energy reduction with little area increase. Finally, we obtain the optimal low power coding for benchmarks of small size from an integer linear programming formulation. We find that the POW3-encoded original FSMs are 27.0% worse than the optimal, but this number drops to 6.7% when we apply POW3 to the re-engineered FSMs.

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Re-encoding for low power state assignment of FSMs

Cited by 11 publications

References 12 publications

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

Guaranteeing testability in re-encoding for low power

FSM re-engineering and its application in low power state encoding

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