RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

Das, Shidhartha; Tokunaga, Carlos; Pant, Sanjay; Ma, Wei-Hsiang; Kalaiselvan, S. A.; Lai, Kuan-Yu; Bull, David; Blaauw, David

doi:10.1109/jssc.2008.2007145

Cited by 484 publications

(265 citation statements)

References 16 publications

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“…The most prominent techniques include TMR, BISER, Razor, GRAAL, Razor II and information redundancy [5,6,7,8,9,14]. TMR and BISER techniques employ hardware redundancy to mask hard errors and/or SEU at latch and flip-flop outputs.…”

Section: A Fault-tolerance In Logic Circuitsmentioning

confidence: 99%

“…These circuits are combined of combinational logic and sequential elements such as latches and flip-flops. Different techniques have been proposed to protect the sequential part from hard errors and/or SEUs [5,6,7,8,9]. Some of these techniques are also efficient for SETs and timing errors that arrived at the combinational part of logic circuits [7,8].…”

Section: Introductionmentioning

confidence: 99%

“…Different techniques have been proposed to protect the sequential part from hard errors and/or SEUs [5,6,7,8,9]. Some of these techniques are also efficient for SETs and timing errors that arrived at the combinational part of logic circuits [7,8]. Besides, in order to protect this part from hard errors, Triple Modular Redundancy (TMR) architecture has been proven to be an efficient method [10,11].…”

Section: Introductionmentioning

confidence: 99%

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A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

et al. 2014

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This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kinds of errors in combinational part of logic circuits and thus, can be combined with advanced SEU protection techniques for sequential elements while reducing the power consumption. The proposed architecture combines different types of redundancies: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error correction. Moreover, it uses a pseudo-dynamic comparator for SET and timing errors detection. Besides, the proposed method also aims to reduce power consumption of fault-tolerant architectures while keeping a comparable area overhead compared to existing solutions. Results on the largest ISCAS'85 and ITC'99 benchmark circuits show that our approach has an area cost of about 3% to 6% with a power consumption saving of about 33% compared to TMR architectures. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by Springer Science+Business Media New York.

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Section: A Fault-tolerance In Logic Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

et al. 2014

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“…The in-situ error detection and correction (EDAC) techniques [4,5,6,7,8,9,10,11,12,13] are proposed to eliminate the timing margins. They monitor timing violations by specially designed circuits, and then take measures to recover functionality of the design if such a violation occurs.…”

Section: Introductionmentioning

confidence: 99%

“…They monitor timing violations by specially designed circuits, and then take measures to recover functionality of the design if such a violation occurs. Examples of EDAC techniques include Razor [3,4,5,9], TIMBER [14], TDTB [6], DSTB [6,8], time borrowing [10,12,14], and etc. These techniques either correct timing errors with large cycle penalty, which in return degrades energy efficiency and throughput [10,15]; or require massive hardware cost and high design complexity to reduce the penalty, which makes them unsuitable for commercial processors [16].…”

Section: Introductionmentioning

confidence: 99%

Light-weight one-cycle timing error correction based on hardware software co-design

Ding

Yan

et al. 2016

IEICE Electron. Express

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A light-weight one-cycle EDAC (timing error detection and correction) technique is proposed to eliminate timing margins resulting from process, voltage, temperature and aging (PVTA) variations. The collaborative approach applies TEDPI (timing error deletion programming interface) to pre-detect most of the errors through an offline error prediction model, and pre-correct them at compilation time by using a specially designed error avoidance instruction. Experimental results based on a three-stage commercial processor show that TEDPI has improved peak performance of the traditional EDAC system by 15.6% and reduced the energy consumption by 4.4% with less than 0.71% area overhead.

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Embedded Systems Design with FPGAs

Athanas¹,

Pnevmatikatos²,

Sklavos³

2013

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The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein.

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RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

Cited by 484 publications

References 16 publications

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

Light-weight one-cycle timing error correction based on hardware software co-design

Embedded Systems Design with FPGAs

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