Rational Sampling Rate Converter using Coefficient Symmetry

Mehra, Rajesh; Singh, Vandita

doi:10.5120/ijca2015906795

Cited by 2 publications

(2 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Design option #4 uses the same linear projection direction d 1 that was used in design option #1. The corresponding projection matrix is given by (22). The PE index associated with a point p in the DG is given by (23).…”

Section: Design Option #4: Using S 2 = [1 1] and D 1 = [1 0] Tmentioning

confidence: 99%

See 1 more Smart Citation

Decimator systolic arrays design space exploration for multirate signal processing applications

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained that combined the antialiasing filter and the downsampler. Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation and compared with the other two well known decimator designs; namely, conventional design, in which the antialiasing filter is followed by a downsampling and the polyphase design, in which a commutator is followed by the polyphase antialiasing filter. Fieldprogrammable gate array implementations for the proposed and the other two designs confirm that the proposed decimator implementation outperforms in terms of area, speed, and power as the decimation factor increases regardless of the number of FIR filter coefficients.

show abstract

Section: Design Option #4: Using S 2 = [1 1] and D 1 = [1 0] Tmentioning

confidence: 99%

“…Mehra and Singh [22] proposed an efficient structure for rational sampling rate converter by combining interpolator and decimator with a low‐pass filter.…”

Section: Introduction and Related Workmentioning

confidence: 99%