Rapid thermal oxidation of GeSi strained layers

Nayak, Deepak Kumar; Kamjoo, K.; Woo, J.C.S.; Park, J. S.; Wang, K. L.

doi:10.1063/1.102653

Cited by 91 publications

(31 citation statements)

References 21 publications

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“…ble gate (DG) metal-oxide-semiconductor field effect transistors (MOSFET) [1,2], resonant tunneling devices [3], Si/Ge nanopillars [4,5] and nanowires [6][7][8][9]. Continual technological innovations make it possible to create semiconductor structures with the MOS channel lengths in the order of 10 nm or even smaller.…”

mentioning

confidence: 99%

Application of the R-matrix method in quantum transport simulations

2011

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The paper gives an overview of recently developed method for effective quantum transport simulations in nanoscale electronic devices. In the present formulation the device is treated as a set of independent close subsystems with appropriate low-dimensional basis representations. In continuous transport models, the local R-matrix basis makes it possible to avoid discretization of the device area and achieve a much higher numerical accuracy with a lower computational burden compared to common grid schemes. Furthermore, the local basis representation provides a suitable framework for studying ionized impurity scattering by adjusting the shape of the device elements and their internal coordinate representation. Non-equilibrium current carrying electronic states are constructed by a recursive propagation scheme such that the major portion of the computation time scales linearly with the device volume. As an illustration, we apply the method to study ionized impurity scattering in a short Si channel.

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confidence: 99%

Application of the R-matrix method in quantum transport simulations

2011

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“…Utilizing the second propagation in Equation set (2) and the orthogonality relations between the various R , A j χ allows one to rewrite Eq. (11) in matrix form,…”

Section: Generalized Eigenvalue Problem For Substrate Basementioning

confidence: 99%

“…The utilization of device physics concepts beyond tranditional CMOS will require the aid of computational tools capable of modelling the quantum transport of a finite number of electrons. A set of devices falling under this category are self-assembled Si/SiGe nanopillars, which utilize Si nanowires oxidized to a certain radius [1] and contain Ge rich cores [2], possibly displaying quantum dot behavior. Prediction of the electrical characteristics of such devices is cleary necessary but requires the development of a three-dimentional (3D), atomistic, full-band simulator.…”

Section: Introductionmentioning

confidence: 99%

Non‐equilibrium Green function implementation of boundary conditions for full band simulations of substrate‐nanowire structures

Rivas

Lake

2003

Physica Status Solidi (b)

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The density of states of a nanowire exhibits peaks at energies in which the individual transverse modes begin to propagate. Under ideal conditions these modes are eigenstates solely determined by the cross sectional size and shape of the nanowire. However, for realistic nanowires, which are grown on semiconductor substrates, the density of states of the subsrate-nanowire structure is dependent on the distance from the nanowire endpoints. Near the substrate, the density of states is is nonzero far below the energy corresponding to the first eigenstate of the ideal nanowire. This initial increase in the density of states occurs at energies near the conduction and valence band edges of the semiconductor substrate on which the nanowire is grown. Away from the substrate, the density of states begins to acquire ideal nanowire characteristics. In the present work this effect is captured by imposing boundary conditions, with properties of bulk material, at the nanowire base. The calculations utilize a first neighbor sp 3 s*d 5 orbital basis within the non-equilibrium Green function formalism.

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“…In past years, silicon dioxide (SiO 2 ) was the most important passivation layer used in III-V MSM-PDs [7]. Various studies on thermal oxidation of SiGe alloys revealed a selective oxidation for silicon, which was accompanied by the rejection of Ge from the oxide and thus resulting in a Ge pile-up at the interface [8][9][10]. Furthermore, misfit dislocations would be generated during the high temperature oxidation process and strain relaxation would occur in the Si/SiGe heterostructure, thus degrading device performance.…”

Section: Introductionmentioning

confidence: 99%