Rapid Prototyping of Clarkson's Lattice Reduction for MIMO Detection

Abstract

This paper presents the field-programmable gate array (FPGA) implementation of a variant of the Lenstra-Lenstra-Lovász (LLL) lattice reduction (LR) algorithm, known as the Clarkson's Algorithm (CA), and its application to uncoded multiple input-multiple output (MIMO) detection. The CA provides practically the same performance as the LLL algorithm while having a considerably lower complexity, especially for MIMO systems with a large number of transmit and receive antennas. The algorithm has been implemented in real-time using a rapid prototyping methodology, greatly reducing its development time. Implementation results indicate that the variable complexity and the sequential nature of LR algorithms, like the CA, remain their main drawbacks from an implementation point of view.

A Digital Signal Processing Architecture for Soft-Output MIMO Lattice Reduction Aided Detection

“…However this implementation only considers slower off-the-shelf FPGA components, including the use of square root and division operations that have not been optimized. The FPGA and application-specific integrated circuit (ASIC) implementation [34] claims to achieve a "fivefold improvement in terms of throughput at the cost of only slightly more FPGA resources" over [26] and [32]. This work uses CORDIC units along with a modification of the LLL algorithm by replacing the size-reduction criterion with the reverse Siegel condition.…”

“…For this reason we are unable to provide a direct comparison of our architecture with previously published work. Nevertheless, it is still possible to compare our implementation with three state-of-the-art VLSI implementations of hard-output LRAD-based MIMO detectors [32], [26], [34].…”

“…The field-programmable gate array (FPGA) implementation of [32] implements the Clarkson's algorithm variant of LLL [33]. However this implementation only considers slower off-the-shelf FPGA components, including the use of square root and division operations that have not been optimized.…”

High performance lattice reduction on heterogeneous computing platform

“…Implementations that make use of LR to improve the detection performance of multiple antenna systems can be found in [3,8,13,16]. In [16], an LR-aided symbol detector for multiple-input multipleoutput (MIMO) and orthogonal frequency division multiple access (OFDMA) is implemented using 65 nm ASIC technologies.…”

“…In [16], an LR-aided symbol detector for multiple-input multipleoutput (MIMO) and orthogonal frequency division multiple access (OFDMA) is implemented using 65 nm ASIC technologies. A field-programmable gate array (FPGA) implementation of a variant of the LLL algorithm, the Clarkson's algorithm, is presented in [3], whose main benefit is the computational complexity reduction without significant performance loss in MIMO detection. More recently, [8] makes use of a Xilinx XC4VLX80-12 FPGA for implementing LR-aided detectors, whereas [13] uses an efficient VLSI design based on a pipelined architecture.…”