Rapid, low-power loop execution in a network of functional units

Tziouvaras, Athanassios; Dimitriou, Georgios

doi:10.1145/2491845.2491859

Cited by 1 publication

(3 citation statements)

References 14 publications

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“…Loop acceleration is an issue which has troubled designers a lot during the last decade [6][9][12] [15]. A proficient way to reduce latency in a loop is the execution of such a loop in an architecture supporting many functional units.…”

Section: Similar Work and Motivationmentioning

confidence: 99%

“…Details on the architecture back end and the functional unit nodes, as well as on the rapid loop execution mechanism that is of key importance for this architecture can be found in [15]. The architecture implements a MIPS-like RISC instruction set with extensions that will be reviewed in the following section.…”

Section: A Short Review Of the Processor Modelmentioning

confidence: 99%

“…These instructions are either memory or branch instructions, and although they have been presented adequately in [15], some changes justify a more detailed review.…”

Section: Instruction Set Extensionsmentioning

confidence: 99%

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Performance and power simulation of a functional-unit-network processor with simplescalar and wattch

Kalaitzidis

Dimitriou

Stamoulis

et al. 2015

Proceedings of the 19th Panhellenic Conference on Informatics

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Loop acceleration is a means to enhance performance of a singleor multiple-issue microprocessor core. A new edge-like processor architecture incorporates a loop accelerator directly in the out-oforder back end of the processor, forming an extended hypercube interconnected network of functional unit nodes. In this work, we have simulated a full processor pipeline of our architecture in a high-level language. In particular, we have extended the Simplescalar, a well-known processor simulator, to include our multifunctional-unit back-end design, and to support our special instructions for loop acceleration. Thus, instructions forming qualified loops are scheduled and dispatched only once for execution, remaining in the back end for all loop iterations, interchanging values in a data-flow fashion. We have also utilized the Wattch power estimation tool, which has been traditionally coupling Simplescalar to produce an estimation of power consumption during simulation, to show that our design results in significant power savings. Since loop instructions reside in the functional unit nodes during loop execution, all front end of the pipeline is turned off and the register file and the instruction cache are kept at low power at that time. Experiments conducted include simulating execution of small loop-based benchmarks from the Livermore loops, as well as longer real-life code taken from open-source mpeg video compression codes. All experiments exhibit the expected performance and power consumption improvements, verifying earlier performance measurements on the HDL model of the back end.

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Section: Similar Work and Motivationmentioning

confidence: 99%

Section: A Short Review Of the Processor Modelmentioning

confidence: 99%