Rapid Instruction Decoding for IA-32

Klimiankou, Yauhen

doi:10.1007/978-3-030-37487-7_1

Cited by 2 publications

(5 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Since we are concerned with automatically generated decoders, we will not consider manual decoders [9,10,18] that are traditionally implemented as nested conditionals. Nor will we deal with decoder generators that require human intervention or data-mining in pregrouping the instructions or providing extra semantic information [11][12][13]17].…”

Section: Functional Analysis Of Decoder Decision Tree Algorithmsmentioning

confidence: 99%

Functional Analysis And Performance Evaluation Of Decoder Decision Tree Generation Algorithms

Tadros

2023

ECMS 2023 Proceedings Edited by Enrico Vicario, Romeo Bandinelli, Virginia Fani, Michele Mastroianni

View full text Add to dashboard Cite

Instruction decoders are indispensable components of instruction set simulators and processor toolchains. The lengthy and elaborate manual implementation of decoders can be greatly alleviated by decoder generation tools. These need to handle the rising complexity of modern instruction sets, notably irregularities such as non-uniform opcodes and logic propositions on bit fields. In addition, decoder generators need to provide cost-optimized solutions, as the efficiency of the decoding module can have a substantial effect on the overall performance. This paper analyzes five published algorithms for decoder generators from two perspectives: First, in terms of functionality, we systematically assess how each tool handles different properties of modern instruction sets, highlighting properties that are challenging, unhandled by current algorithms or even result in functionally erroneous decoders. Second, we challenge seemingly intuitive definitions of decoder optimality using a sophisticated model of decision tree cost. We validate this analytical model against an experimental performance evaluation of generated decoders for SPARC, MIPS32 and ARMv7 platforms. For our analysis, we implemented all five algorithms after correcting the discovered conceptual errors and extending them to handle the above-mentioned ISAs. Our work reveals that state-of-the-art decoder generation tools are unable to fully and correctly handle complex ISAs and adopt an erroneous notion of optimality.

show abstract

Section: Functional Analysis Of Decoder Decision Tree Algorithmsmentioning

confidence: 99%

Functional Analysis And Performance Evaluation Of Decoder Decision Tree Generation Algorithms

Tadros

2023

ECMS 2023 Proceedings Edited by Enrico Vicario, Romeo Bandinelli, Virginia Fani, Michele Mastroianni

View full text Add to dashboard Cite

show abstract

“…The opcode is a bytecode-level representation of the instruction, that identifies it for the CPU (as well as for our emulator) and thus must also be used as a part of the code generation. This is known as "instruction decoding" [Kli19b]. "Inlining" is the name we use to refer to the "true" compilation where an input instruction is compiled to one or more individual atomic bytecode instructions of the target platform.…”

Section: Main Challenges and Approachesmentioning

confidence: 99%

“…Determining which instruction to execute next ("instruction decoding" [Kli19b]), in a broad sense, is just parsing [ZB14]. Having the knowledge about the general syntactic structure of each instruction (its length in bytes, positions of instructiondefining opcode bytes and their values) makes this a trivial generative task, with some handling of corner cases-e.g., the EXECUTE instruction mentioned above, does not return to the original call location if the executed instruction is a branching one.…”

Section: Semantic Steps Modellingmentioning

confidence: 99%

“…On a more technical side, Klimiankou recently published an interesting story centred primarily on parsing of instructions for IA-32 (which is the Intel assembler as opposed to our IBM assembler, but the two are very much alike) [Kli19b]. In our work his "instruction decoding" corresponds to the emulator figuring out at runtime which instruction to execute next and how to turn its bits into meaningful entities corresponding to its arguments in terms of which its core semantics is expressed.…”

Section: Related Workmentioning

confidence: 99%

“…In our work his "instruction decoding" corresponds to the emulator figuring out at runtime which instruction to execute next and how to turn its bits into meaningful entities corresponding to its arguments in terms of which its core semantics is expressed. Klimiankou managed to build the fastest decoder for IA-32 commands [Kli19b] and was able to leverage it to migrate from switch-based dispatch (that we also use) to concurrent threaded code [Kli19a].…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Modelling of Language Syntax and Semantics: The Case of the Assembler Compiler.

Zaytsev¹

2020

JOT

View full text Add to dashboard Cite

Application of software language technologies, whether analytical, transformational, or generational, in an industrial context is usually a taxing endeavour, with high demands in qualification levels of developers involved in it. Yet, if applied successfully, in the right places and with the right amount of effort, they promise high returns in terms of optimisation, effectiveness, validity and verifiability. In this paper, we report on our experience on writing a compiler for a complex second generation legacy programming language originally intended to be used on a mainframe. The business case for this product deals with companies migrating their software systems off the mainframe to cloud native or PC. Leveraging the documentation, available domain knowledge, several sample projects and a test suite, as well as several proprietary DSLs, we successfully modelled syntax and semantics of hundreds of instructions of that language, to the point of producing a compiler with a very limited group of compiler developers in limited time. The compiler is currently deployed at some of our customers and has received a top technology award from Microsoft.This report is meant to serve as a sample snapshot of how compilers can be built in the industry with software language engineering techniques. Traditional problems of compiler construction such as parsing or code optimisation either did not present a noticeable challenge or did not manifest themselves altogether in the course of this project, but MDE matters such as model transformation, modular design, the use of DSLs and meta-tools, were a constant concern. The focus of the report is in truthful representation of the domain as well as the details of the project, on reflection of the choices that were taken or could have been taken in the meantime, and on lessons learnt during the project.

show abstract

Rapid Instruction Decoding for IA-32

Cited by 2 publications

References 1 publication

Functional Analysis And Performance Evaluation Of Decoder Decision Tree Generation Algorithms

Functional Analysis And Performance Evaluation Of Decoder Decision Tree Generation Algorithms

Modelling of Language Syntax and Semantics: The Case of the Assembler Compiler.

Contact Info

Product

Resources

About