Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms

McAllister, John; Woods, Roger; Reilly, D.; Fischaber, Scott; Hasson, Robert G.

doi:10.1007/11512622_44

Cited by 6 publications

(8 citation statements)

References 7 publications

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“…In Abhainn, the notion is extended to Multidimensional Arrayed Synchronous Dataflow (MASDF), where the notion of actors and arcs are extended to arrays or families [4,5]. This allows the designer to explore various levels of parallelism in the algorithm by manipulating the sizes of the arrays and trading off the number of actors with the processing characteristics of each to affect implementation optimisation.…”

Section: Muirmentioning

confidence: 98%

“…Whilst the native on-chip resources to realise these systems are in place and approaches for system level design of embedded systems are increasing in number [1, 2,3], there is a dearth of suitable design technology in the forms of both tools and methodologies for rapidly implementing these systems on heterogeneous FPGAcentric embedded platforms. The Abhainn approach [4] attempts to fulfil these requirements. One major challenge is the generation, transformation and optimisation of dedicated hardware implementations of algorithms whilst incorporating pre-designed Intellectual Property (IP) cores to support complex functionality.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Muir Hardware Synthesis for Multimedia Applications

Fischaber

McAllister

Woods

et al. 2006

2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia

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This paper describes the Muir hardware synthesis process used in the Abhainn design flow for optimisation and implementation of applications on FPGA-centric platforms and specifically its use for multimedia applications. Demonstrated are transformations available at the algorithmic level for an MPEG-2 encoder to reduce the memory usage and increase the throughput of the system. Also examined is the effect manipulations of the algorithm have on the final hardware architecture. Implementation of the encoder shows that results derived from a system level design approach are comparable with those derived from hand-coded implementations.

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Section: Muirmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

Muir Hardware Synthesis for Multimedia Applications

Fischaber

McAllister

Woods

et al. 2006

2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia

Self Cite

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“…Whilst UML profiles for embedded systems have begun appearing, they are still lacking in necessary support for targeting modern heterogeneous platforms. For these reasons, C and UML will not be discussed in this paper, but projects such as PeaCE [4], Owen [15], CAL [14], Compaan/Laura [12], and Daedalus [13] fall into the later two categories, which can be referred to as actor-orientated design. With respect to hardware realisation, they take a similar approach, using networks of cores generally connected by simple interconnections, but the design flows and the MoCs used to describe the algorithms differ.…”

Section: Existing Workmentioning

confidence: 99%

“…The final implementation should then be derived from this model, ideally with little effort required on the part of the designer. The need for these high level design tools to translate functional models into hardware has spurred research using a number of models and languages, including C and subsets of C [9,10], UML [11], process networks [12,13], and dataflow networks [4,14,15]. Using C, the sequential nature of the programming environment means that parallelism implicit to the algorithm can be lost when modelling it, and also features of the resulting architecture can be unintentionally dictated by the code thereby proving restrictions in the creation and exploration of the architecture from a 'pure' representation of the algorithm.…”

Section: Existing Workmentioning

confidence: 99%

SoC Memory Hierarchy Derivation from Dataflow Graphs

Fischaber

Woods

McAllister

2009

J Sign Process Syst

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Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.

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“…The need for high level design tools has spurred research using various models of computation including C and subsets of C [5] [6], UML [7], process networks [8] and dataflow networks [3] [9]. The first two are out of the scope of this paper, but projects such as PeaCE [3], Owen [9] and Compaan/Laura [8] all fall into the latter two categories.…”

Section: Existing Workmentioning

confidence: 99%