Rapid design of area-efficient custom instructions for reconfigurable embedded processing

Lam, Siew-Kei; Srikanthan, Thambipillai

doi:10.1016/j.sysarc.2008.06.003

Cited by 31 publications

(41 citation statements)

References 32 publications

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“…Other related and complementary work includes: 1) use of local memories for improving the performance of custom instructions [25], [29]; 2) datapath merging [30] and combinational equivalence checking [31] techniques to improve resource sharing; 3) synthesis of custom instructions targeting field-programmable systems [32], [33], including support for run-time reconfiguration [34], [35]; and 4) transparent integration of custom instructions with a general-purpose processsor [36].…”

Section: Related Workmentioning

confidence: 99%

FISH: Fast Instruction SyntHesis for Custom Processors

Atasu

Luk

Mencer

et al. 2012

IEEE Trans. VLSI Syst.

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Abstract-This paper presents Fast Instruction SyntHesis (FISH), a system that supports automatic generation of custom instruction processors from high-level application descriptions to enable fast design space exploration. FISH is based on novel methods for automatically adapting the instruction set to match an application in a high-level language such as C or C. FISH identifies custom instruction candidates using two approaches: 1) by enumerating maximal convex subgraphs of application data flow graphs and 2) by integer linear programming (ILP). The experiments, involving ten multimedia and cryptography benchmarks, show that our contributed algorithms are the fastest among the state-of-the-art techniques. In most cases, enumeration takes only milliseconds to execute. The longest enumeration run-time observed is less than six seconds. ILP is usually slower than enumeration, but provides us with a complementary solution technique. Both enumeration and ILP allow the use of multiple different merit functions in the evaluation of data-flow subgraphs. The experiments demonstrate that, using only modest additional hardware resources, up to 30-fold performance improvement can be obtained with respect to a single-issue base processor.

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Section: Related Workmentioning

confidence: 99%

FISH: Fast Instruction SyntHesis for Custom Processors

Atasu

Luk

Mencer

et al. 2012

IEEE Trans. VLSI Syst.

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“…The potential benefits of instruction set extension have led to numerous amount of research work that focuses on generating custom instructions from a given application (see [5] for a list of references). In order to select custom instructions for different runtime configurations, temporal partitioning must be performed to divide the design into mutually exclusive configurations such that the computational resource requirement of each configuration is less than or equal to the reconfigurable resource capacity of the RFU.…”

Section: A Related Workmentioning

confidence: 99%

“…The IR serves as input to the Custom Instruction Generation stage to identify a set of custom instruction candidates. Details of the Custom Instruction Generation stage can be found in [5]. The hardware area-time information of the custom instruction candidates are then rapidly estimated without undergoing time-consuming hardware implementation.…”

Section: B Our Workmentioning

confidence: 99%

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Hierarchical Loop Partitioning For Rapid Generation of Runtime Configurations

Lam

Deng

Srikanthan

et al. 2009

2009 Fourth International Conference on Embedded and Multimedia Computing

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Runtime reconfiguration provides an efficient means to reduce the hardware cost, while satisfying the performance, flexibility and power requirements of embedded systems. The growing complexity of the applications necessitates methods that can rapidly identify a suitable set of configurations by splitting the computational structures into temporal partitions in order to evaluate the benefits of runtime reconfiguration early in the design cycle. In this paper, we present a hierarchical loop partitioning strategy that reduces the complexity of the search space for determining the runtime custom instruction configurations for reconfigurable processors. Experimental results show that the proposed partitioning strategy can lead to an average and maximum performance gain of over 14% and 31% respectively when compared to a recently reported technique. In addition, when compared to the existing technique, the proposed partitioning method has significantly lower runtime in many of the cases considered.

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“…Customizing the instruction set of a base processor is emerging as a key design methodology in new extensible embedded processors exploiting both programmability and efficiency. In these methods the base processor is extended with custom functional units that provide application-specific instructions [1], [2], [3], [4]. Major concerns in the design of a customized embedded processor are computational performance, area efficiency, and limited productivity of the designers.…”

Section: Introductionmentioning

confidence: 99%

Vulnerability Analysis for Custom Instructions

Azarpeyvand

Salehi

Fakhraie

2012

2012 15th Euromicro Conference on Digital System Design

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Today circuits are becoming more vulnerable to electronic noises and reliable system design has emerged as a key challenge to embedded system design. Logic fault in terms of soft errors or transient faults are now a serious problem for embedded processors. Recent developments in customized embedded processors significantly focus on improving the performance and area of the processor by augmenting it with application specific custom functional units that implement custom instructions. This paper analyzes the effect of type, order, and bit-width of the operations of different custom instruction sub-graphs on the vulnerability of extensible processors. We have developed a framework for studying the effects of different operations and their dependencies on overall vulnerability of the custom functional units and our experiments show that, in most cases, similar custom functional units could have different vulnerabilities to soft errors. Our approach enables designers to optionally constrain the operand types and also the custom functional unit structure to reach an acceptable vulnerability.

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Rapid design of area-efficient custom instructions for reconfigurable embedded processing

Cited by 31 publications

References 32 publications

FISH: Fast Instruction SyntHesis for Custom Processors

FISH: Fast Instruction SyntHesis for Custom Processors

Hierarchical Loop Partitioning For Rapid Generation of Runtime Configurations

Vulnerability Analysis for Custom Instructions

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