Rapid Cycle-Accurate Simulator for High-Level Synthesis

Chi, Yuze; Choi, Y.; Cong, Jason; Wang, Jie

doi:10.1145/3289602.3293918

Cited by 12 publications

(10 citation statements)

References 19 publications

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“…Some simulation statistics are not reported by the designers (N/A). keypair [58], gsm [59], HLSCNN [60], FlexNLP [61], Dataflow [62], and Opticalflow [63] do not feature any subaccelerators with a batch size greater than one. One OOB bug was found in gsm and one initialization bug was found in keypair.…”

Section: Appendix D Results (Extended)mentioning

confidence: 99%

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay,

Lonsing,

Piccolboni

et al. 2021

Preprint

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Hardware accelerators (HAs) are essential building blocks for fast and energy-efficient computing systems. Accelerator Quick Error Detection (A-QED) is a recent formal technique which uses Bounded Model Checking for pre-silicon verification of HAs. A-QED checks an HA for self-consistency, i.e., whether identical inputs within a sequence of operations always produce the same output. Under modest assumptions, A-QED is both sound and complete. However, as is well-known, large design sizes significantly limit the scalability of formal verification, including A-QED. We overcome this scalability challenge through a new decomposition technique for A-QED, called A-QED with Decomposition (A-QED 2 ). A-QED 2 systematically decomposes an HA into smaller, functional sub-modules, called sub-accelerators, which are then verified independently using A-QED. We prove completeness of A-QED 2 ; in particular, if the full HA under verification contains a bug, then A-QED 2 ensures detection of that bug during A-QED verification of the corresponding subaccelerators. Results on over 100 (buggy) versions of a wide variety of HAs with millions of logic gates demonstrate the effectiveness and practicality of A-QED 2 . This article will appear in the proceedings of Formal Methods in Computer-Aided Design (FMCAD 2021).

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Section: Appendix D Results (Extended)mentioning

confidence: 99%

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Chattopadhyay,

Lonsing,

Piccolboni

et al. 2021

Preprint

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“…Performance counters are inserted to the accelerator to collect the relevant metrics. We implement SPLAG using an open-source extension to HLS C++, TAPA [10], to leverage the convenient peeking interfaces, fast software simulation [6,12], asynchronous memory interfaces, simplified host-kernel interfaces, and coarse-grained floorplanning [26,27]. Our implementation targets the Alveo U280 board with 32 high-bandwidth memory (HBM) channels.…”

Section: Discussionmentioning

confidence: 99%

Accelerating SSSP for Power-Law Graphs

Chi

Guo

Cong

2022

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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The single-source shortest path (SSSP) problem is one of the most important and well-studied graph problems widely used in many application domains, such as road navigation, neural image reconstruction, and social network analysis. Although we have known various SSSP algorithms for decades, implementing one for largescale power-law graphs efficiently is still highly challenging today, because ① a work-efficient SSSP algorithm requires priority-order traversal of graph data, ② the priority queue needs to be scalable both in throughput and capacity, and ③ priority-order traversal requires extensive random memory accesses on graph data.In this paper, we present SPLAG to accelerate SSSP for powerlaw graphs on FPGAs. SPLAG uses a coarse-grained priority queue (CGPQ) to enable high-throughput priority-order graph traversal with a large frontier. To mitigate the high-volume random accesses, SPLAG employs a customized vertex cache (CVC) to reduce off-chip memory access and improve the throughput to read and update vertex data. Experimental results on various synthetic and realworld datasets show up to a 4.9× speedup over state-of-the-art SSSP accelerators, a 2.6× speedup over 32-thread CPU running at 4.4 GHz, and a 0.9× speedup over an A100 GPU that has 4.1× power budget and 3.4× HBM bandwidth. Such a high performance would place SPLAG in the 14th position of the Graph 500 benchmark for data intensive applications (the highest using a single FPGA) with only a 45 W power budget. SPLAG is written in high-level synthesis C++ and is fully parameterized, which means it can be easily ported to various different FPGAs with different configurations. SPLAG is open-source at https://github.com/UCLA-VAST/splag. CCS CONCEPTS• Theory of computation → Shortest paths; • Computer systems organization → Reconfigurable computing; High-level language architectures.

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“…is problem was also pointed out in [8]. In order to run soware simulation correctly, the programmer can change the source code to run tasks in multiple threads for so ware simulation, but doing so requires the same piece of task instantiation code to be wri en twice for synthesis and simulation, reducing productivity.…”

Section: Motivating Examplementioning

confidence: 99%

“…However, they may perform poorly due to the ine ciency of inter-thread communication and context switch handled by the operating system. e FLASH simulator [8,12] proposed an alternative to the above, which relies on the HLS scheduling information to mimic the RTL FSM. While this simulation approach itself is faster than multi-thread simulators, generating simulation executable becomes slower due to the need of the HLS scheduler output for cycle-accuracy, which is not needed for correctness veri cation.…”

Section: So Ware Simulationmentioning

confidence: 99%

Extending High-Level Synthesis for Task-Parallel Programs

Chi

Guo

Lau

et al. 2021

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for eld-programmable gate array (FPGA) accelerators in many application domains in recent years, thanks to its competitive quality of result (QoR) and short development cycle compared with the traditional register-transfer level (RTL) design approach. Yet, limited by the sequential C semantics, it remains challenging to adopt the same highly productive high-level programming approach in many other application domains, where coarse-grained tasks run in parallel and communicate with each other at a ne-grained level. While current HLS tools support taskparallel programs, the productivity is greatly limited in the code development, correctness veri cation, and QoR tuning cycles, due to the poor programmability, restricted so ware simulation, and slow code generation, respectively. Such limited productivity o en defeats the purpose of HLS and hinder programmers from adopting HLS for task-parallel FPGA accelerators.In this paper, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, universal so ware simulation, and fast code generation to overcome these limitations. Experimental results based on a wide range of real-world task-parallel programs show that, on average, the lines of kernel and host code are reduced by 22% and 51%, respectively, which considerably improves the programmability. e correctness veri cation and the iterative QoR tuning cycles are both greatly accelerated by 3.2× and 6.8×, respectively.

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Rapid Cycle-Accurate Simulator for High-Level Synthesis

Cited by 12 publications

References 19 publications

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition

Accelerating SSSP for Power-Law Graphs

Extending High-Level Synthesis for Task-Parallel Programs

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