Ranking process parameter association with low yield wafers using spec-out event network analysis

Yang, Juhee; Lee, Seung-Kyung; Kang, Seokho; Cho, Sungzoon; Lee, Younghak; Park, Hae Sang

doi:10.1016/j.cie.2017.09.036

Cited by 3 publications

(3 citation statements)

References 16 publications

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“…Khakifirooz, Chien and Chen (2018) developed a Bayesian inference approach that integrates Gibbs sampling and Cohen's kappa coefficient. Chen et al (2017) proposed a framework based on least absolute shrinkage and selection operator and RF to screen critical process parameters in addition to critical process stages and machines, while Yang et al (2017) adopted the page-rank algorithm to the event network for ranking process parameters associated with row-yield wafers. Moreover, Chien and Chuang (2014) proposed a root cause analysis framework for sub-batch processing systems while Chouichi et al (2020) analyzed the quality mismatching issue among parallel chambers using FDC and metrology data.…”

Section: Related Workmentioning

confidence: 99%

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A sensor data mining process for identifying root causes associated with low yield in semiconductor manufacturing

Kim

Cho

et al. 2023

DTA

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PurposeThe purpose of this paper is to identify the root cause of low yield problems in the semiconductor manufacturing process using sensor data continuously collected from manufacturing equipment and describe the process environment in the equipment.Design/methodology/approachThis paper proposes a sensor data mining process based on the sequential modeling of random forests for low yield diagnosis. The process consists of sequential steps: problem definition, data preparation, excursion time and critical sensor identification, data visualization and root cause identification.FindingsA case study is conducted using real-world data collected from a semiconductor manufacturer in South Korea to demonstrate the effectiveness of the diagnosis process. The proposed model successfully identified the excursion time and critical sensors previously identified by domain engineers using costly manual examination.Originality/valueThe proposed procedure helps domain engineers narrow down the excursion time and critical sensors from the massive sensor data. The procedure's outcome is highly interpretable, informative and easy to visualize.

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Section: Related Workmentioning

confidence: 99%

“…However, for various reasons, an ideal environment is not reached. Consequently, not all chips have undergone an identical recipe function as desired (Yang et al , 2017).…”

Section: Introductionmentioning

confidence: 99%

A sensor data mining process for identifying root causes associated with low yield in semiconductor manufacturing

Kim

Cho

et al. 2023

DTA

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“…Yang et al proposed a novel approach that incorporates the interactions among spec-out events using spec-out event network analyses with time-series process sensor data such as temperature, pressure, and voltage data [20]. Lee et al proposed a convolutional neural network (CNN) model, in which a receptive field tailored to multivariate sensor signals slides along the time axis, to extract fault features.…”

Section: B Sequential Research In Semiconductor Manufacturingmentioning

confidence: 99%

Wafer Edge Yield Prediction Using a Combined Long Short-Term Memory and Feed- Forward Neural Network Model for Semiconductor Manufacturing

Kim

2020

IEEE Access

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In semiconductor manufacturing, maintaining a high yield and ensuring accurate yield prediction are considerably important for improving productivity, customer satisfaction, and enhancing profitability. Despite its importance and merits, achieving wafer yield prediction with high quality and accuracy is challenging. In this paper, we propose a method for wafer edge yield prediction using a combined long short-term memory (LSTM) and feed-forward neural network (FFNN) model. Unlike previous research, we focus on the edge yield because of the higher yield loss at the wafer edge. The combined LSTM-FFNN model uses a dataset divided into two types according to data characteristics. Timeseries data are used in the case of LSTM, and non-time-series data are fed into the FFNN. When preparing the time-series data, comprising data related to the equipment and chambers, data of different chambers do not overlap, thereby rendering them as independent entities. The proposed model outperforms other models in terms of all evaluation metrics. The coefficient of determination of the proposed combined LSTM-FFNN model is 34.14%, which is almost 13% higher than that of the other compared models on average.

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Adaptive fault detection framework for recipe transition in semiconductor manufacturing

Shim

Cho

Kum

et al. 2021

Computers & Industrial Engineering

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Ranking process parameter association with low yield wafers using spec-out event network analysis

Cited by 3 publications

References 16 publications

A sensor data mining process for identifying root causes associated with low yield in semiconductor manufacturing

A sensor data mining process for identifying root causes associated with low yield in semiconductor manufacturing

Wafer Edge Yield Prediction Using a Combined Long Short-Term Memory and Feed- Forward Neural Network Model for Semiconductor Manufacturing

Adaptive fault detection framework for recipe transition in semiconductor manufacturing

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