Random Yield Model in Integrated Circuit Design

Abstract

As feature dimension of integrated circuits (IC) come into nanometer nodes, yield problems caused by random defects get worse. Even with advanced process techniques, the yield could not achieve 100%. Accurate prediction of yield can point out the direction of process optimization, shorten the production cycle, reduce the production cost, and then increase profits. In this paper, some kinds of random defects which can influence random yield are summarized. Then some widely used yield models are outlined and the drawbacks of these models are analyzed. At last, an improved yield model is proposed with the combination of Poisson model and negative binominal model. This model which takes distributions of random defects into consideration is more flexible and accurate. It can be seen from the simulation results that comparing to those existing models, the improved model indeed has higher fidelity and more flexibility.