Random variability modeling and its impact on scaled CMOS circuits

Abstract

Random variations have been regarded as one of the major barriers on CMOS scaling. Compact models that physically capture these effects are crucial to bridge the process technology with design optimization. In this paper, 3-D atomistic simulations are performed to investigate fundamental variations in a scaled CMOS device, including random dopant fluctuation (RDF), line-edge roughness (LER), and oxide thickness fluctuation (OTF). By understanding the underlying physics and analyzing simulation results, compact models for random threshold (V th ) variations are developed. The models are scalable with device specifications, enabling quantitative analysis of circuit performance variability in future technology nodes. Using representative circuits, such as the inverter chain and SRAM cell, key insights are extracted on the trend of variability, as well as the implications on robust design.

Incremental computation of delay fault detection probability for variation-aware test generation

“…The gate model for this approach conforms to the Verilog HDL [23] standard, but instead of real numbers, every delay value X of a gate has a normal distribution with variance var(X) = (c v E[X]) 2 and mean E[X] equal to the nominal delay value from the standard delay format description of the synthesized circuit. Based on predictions for future process technology nodes [14], a variation coefficient of c v = 0.25 was selected. Interconnect delays and spatial correlations would require the analysis of full chip layouts, which had not been designed to avoid an unnecessary complex experimental setup.…”

“…However, the resulting approximation error is acceptable only for tiny delay variations in the mature and classical manufacturing technology space [14].…”

An analytical approach to efficient circuit variability analysis in scaled CMOS design

“…It is loaded with FO10 and fanin is FO4. Amount of V th variation to be added is calculated using method from [32]. As expected, when input is given to M3 transistor, V th variation in M1 and M3 results in considerable delay variability but variation in M2 transistor has almost no effect.…”

“…This is done by applying V th variation because of each of these factors to the inverter circuit. The variation in V th is calculated using the method in [32] . …”

Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

“…As the transistors minimum size shrinks, the uncertainty due to process variations increases as well as the aging effects become more important [1], [2]. In addition, the transistor size reduction allows the integration of more functions in the die.…”