Random Telegraph Noise Intensification After High-Temperature Phases in 3-D NAND Flash Arrays

Malavena, Gerardo; Giulianini, Mattia; Chiavarone, Luca; Spinelli, A.S.; Compagnoni, Christian Monzio

doi:10.1109/led.2022.3154432

Cited by 10 publications

(4 citation statements)

References 35 publications

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“…This means that polysilicon trap depassivation has a marked dependence on the cell V T level and is almost negligible with respect to charge detrapping for level L2 and, in turn, L1. A similar conclusion is also supported by the RTN intensification results reported in [20] and by the experimental analyses presented in [22].…”

Section: A Results On Fresh (Uncycled) Samplessupporting

confidence: 86%

“…In addition, we recently reported experimental evidence for the growth of the number of active traps in the polysilicon channel of 3D NAND strings over long stretches of time spent at high temperature, due to the depassivation of some microscopic defects in the material. We showed that that growth is responsible for the intensification of random telegraph noise (RTN) [20] and long-term V T instabilities in 3D arrays [21]. Further evidence for the phenomenon was reported in [22], where it was also shown to worsen the cross-temperature (data storage and retrieval carried out at different temperatures) reliability of the array.…”

Section: Introductionmentioning

confidence: 57%

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Analysis of High-Temperature Data Retention in 3D Floating-Gate nand Flash Memory Arrays

Malavena,

Giulianini,

Chiavarone

et al. 2023

IEEE J. Electron Devices Soc.

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In this paper, we present a detailed experimental investigation of high-temperature data retention in 3D floatinggate NAND Flash memory arrays. Data reveal that charge detrapping from the cell tunnel oxide and depassivation of traps in the string polysilicon channel are the physical mechanisms resulting in the most relevant long-term reliability issues for the memory array. On one hand, the two mechanisms give rise to threshold-voltage (V T ) instabilities with similar activation energy and comparable magnitude on fresh devices. On the other hand, polysilicon trap depassivation displays a negligible strengthening with cycling and a more marked dependence on the cell V T level during data retention with respect to charge detrapping. Results must be carefully considered in the reliability assessment of all state-of-the-art and future 3D NAND Flash technology nodes.

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Section: A Results On Fresh (Uncycled) Samplessupporting

confidence: 86%

Section: Introductionmentioning

confidence: 57%

Analysis of High-Temperature Data Retention in 3D Floating-Gate nand Flash Memory Arrays

Malavena,

Giulianini,

Chiavarone

et al. 2023

IEEE J. Electron Devices Soc.

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“…The oscillations observed in the I BL -V WL transcharacteristic at low V BL can hardly be attributed to the modulation of current transport through cell channel by the capture/emission of charge carriers in microscopic defects in the cell gate stack or at the polysilicon grain boundaries [15], [16], [17], [18], [19], [20], [21]. To rule out this possibility, we sampled I BL at low V BL using V WL values in the range corresponding to an oscillation in the trans-characteristic.…”

Section: Resultsmentioning

confidence: 99%

First Evidence of SET-Like Behavior of 3-D NAND Flash Cells in the Deep-Cryogenic Regime

Refaldi,

Malavena,

Giulianini

et al. 2024

IEEE Trans. Electron Devices

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In this article, we report the first experimental investigation of the behavior of the 3-D NAND Flash memory technology in the deep-cryogenic regime (temperature T < 50 K). Clear evidence is provided to demonstrate that, in that T regime, the reduction of the Read bitline voltage gives rise to a paradigm shift in the current-voltage characteristics of the memory cells, consisting of the appearance of single-electron transistor (SET)-like conduction schemes. The phenomenon is traced back to nonuniformities in the electrostatic inversion of cell channel, producing, at that deep-cryogenic T, a landscape of conductive quantum dots separated by energy barriers where electron transport is affected by Coulomb blockade. The results represent a first step toward innovative applications of 3-D NAND Flash memories.

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“…Therefore, the study of ferroelectric-FET (FeFET) with HfO 2 -based ferroelectric materials has become one of the important topics of solid-state electronic devices. In order to meet the requirements of high density and high capacity of NVMs, the thinfilm transistor (TFT) using polycrystalline-silicon (poly-Si) channels has become the mainstream of flash memory [10,11]. Therefore, ferroelectric TFTs (Fe-TFTs) using poly-Si channels have become an important research topic for Fe-NVM to meet the same requirements as conventional flash memory [12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Impacts of pulse conditions on endurance behavior of ferroelectric thin-film transistor non-volatile memory

Cheng-Yu¹,

Su²,

Kao³

et al. 2023

Semicond. Sci. Technol.

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In this work, the ferroelectric thin-film transistor (Fe-TFT) with polycrystalline-silicon (poly-Si) channel and HfZrOx gate dielectric is fabricated to study the characteristics of non-volatile memory (NVM). Significant threshold voltage (VTH) modulation can be achieved with low pulse voltages less than ±3.5 V and pulse widths within 1 μs. In order to achieve the NVM characteristics of low voltage and high speed operation, the impact of the program/erase (PRG/ERS) pulse voltage (VPRG/VERS) and pulse width on endurance is a critical consideration. In the study of the pulse width effect on endurance, it can be observed that the VTH in PRG-state exhibits the wake-up effect at both short and long pulse widths. In addition, with the increase of pulse width, the VTH in the PRG-state exhibits significant fatigue effect and subthreshold swing (SS) degradation effect. For VTH in the ERS-state, the increase of the pulse width also exhibits the fatigue effect and the SS degradation effect, which is dominated by the SS degradation effect at long pulse widths. In the study of the pulse voltage effect on endurance, the increase of VPRG shows the imprint effect that the VTH in either PRG- or ERS-state reveals a decreasing trend. When the VERS increases, the SS of the PRG- and ERS-states is degraded, and the fatigue effect of the PRG-state is enhanced. Moreover, the retention characteristics of poly-Si Fe-TFTs exhibit stable characteristics at both room temperature and 50 oC.

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Random Telegraph Noise Intensification After High-Temperature Phases in 3-D NAND Flash Arrays

Cited by 10 publications

References 35 publications

Analysis of High-Temperature Data Retention in 3D Floating-Gate nand Flash Memory Arrays

Analysis of High-Temperature Data Retention in 3D Floating-Gate nand Flash Memory Arrays

First Evidence of SET-Like Behavior of 3-D NAND Flash Cells in the Deep-Cryogenic Regime

Impacts of pulse conditions on endurance behavior of ferroelectric thin-film transistor non-volatile memory

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