Random errors in MOS capacitors

Using MOS-transistors with floating gate (Neuron MOS or MOS) for building threshold logic is discussed. Two ways of MOS threshold logic implimention -static and clocked -are under consideration. Methodology of MOS circuit design is given. Majority voting gate (MVG) is used as an example of threshold gate with worst conditions for getting a large number of inputs. The possibility of implementing a MVG with a certain number of inputs is the possibility of building a threshold gate with a threshold alterable in real time (from OR to AND-function) with the sum of input weights equal to the number of MVG inputs. The maximum number of threshold gate inputs is estimated depending upon the deviations of the elements dimensions and parameters inside the chip. It is shown that it is difficult to implement a static MOS MVG with a number of inputs more than 10. For the same conditions, the number of inputs of clocked MOS MVG is as large as many tens. A clocked MOS threshold gate with alterable in real-time input weights and threshold is proposed. Delay time and chip area for such a circuits are estimated.

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“…and inverter threshold voltages. As shown in [11], the less the capacitors dimensions, the more the capacity value deviation.…”

Section: Design Methodology Of Mosmentioning

confidence: 99%

The efficiency of neuron-MOS transistors in threshold logic

1999

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“…Lakshmikumar et al [6] suggest that the higher mismatch of P-channel devices is possibly due to higher mobility variations and poorer gate· oxide capacitance matching. We have no explanation for the non 1/../WL mismatch seal- ing, and attempts to explain the measurements with edge variations (see (1]) or long-range (global) parameter variations (3] have failed.…”

Section: Device Dimensionsmentioning

confidence: 99%

“…Shyu et al [1,2] analyze the effect of edge roughness, surface state and implanted charge fluctuations, oxide thickness variations and mobility fluctuations in terms of short range (local) and long range (global) parameter variations. Pelgrom et al [3] introduce a powerful spatial Fourier transform technique to build a general frame in which different transistor geometries can be accommodated.…”

Section: Introductionmentioning

confidence: 99%

Measurement of MOS current mismatch in the weak inversion region

Forti

Wright

1994

IEEE J. Solid-State Circuits

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“…It is therefore important that a circuit designer can incorporate these effects in early simulation stage. A variability-aware design approach needs a right prediction of random variations [4][5][6][7]. The investigation and analyze of these variations using accurate 'atomistic' simulations needs both long times and powerful computational resources [1].…”

Section: Introductionmentioning

confidence: 99%

A Simulation Algorithm for Prediction of Random Variations in Digital Circuits

Shokuhfar¹,

Dideban²,

Moezi³

et al. 2015

IJCA

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A novel simulation algorithm capable of capturing statistical variability manifests in digital design is proposed. The only estimations for the algorithm inputs are the standard deviations of channel length and the gate voltage. Implementing the algorithm for the simulation of propagation delay times of the basic digital building blocks such as inverter, NAND2 and NOR2 circuits gives errors less than 7% against the most accurate results obtained from 'atomistic' HSPICE simulations.

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Random errors in MOS capacitors

Cited by 141 publications

References 2 publications

The efficiency of neuron-MOS transistors in threshold logic

The efficiency of neuron-MOS transistors in threshold logic

Measurement of MOS current mismatch in the weak inversion region

A Simulation Algorithm for Prediction of Random Variations in Digital Circuits

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