Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits

Li, Yiming; Hwang, C. S.; Li, Tien-Yeh

doi:10.1109/ted.2009.2022692

Cited by 57 publications

(24 citation statements)

References 59 publications

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“…We define transistor delay as We consider the situation where the first term is five times larger than the second, which means that is dominant in . Then, we have (44) In advanced design technology, is decreased to 0.6 ps [26]. Then, when , we have , which means the operation frequency is 190 MHz.…”

Section: B Operation Speed Of Adiabatic Logicmentioning

confidence: 99%

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

Nakata

Honda

Makino

et al. 2012

IEEE Trans. Circuits Syst. I

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The stability of a stepwise waveform of an adiabatic charge recycling circuit with tank capacitors is investigated. We propose a new tank capacitor circuit with two-string capacitor arrays. We experimentally confirmed the stability of the five-step waveform from the tank capacitors. The voltage changes of tank capacitors in the experiment are consistent with the simulation. The power consumption is reduced to one-fifth due to the five-step waveform. We analyze the stability using matrix theory. The results prove that the step waveform is stable for any circuit topology. Moreover, we consider the effects of conductors fixed at a certain voltage and floating conductors and confirm the system is stable using matrix theory.

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Section: B Operation Speed Of Adiabatic Logicmentioning

confidence: 99%

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

Nakata

Honda

Makino

et al. 2012

IEEE Trans. Circuits Syst. I

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“…As the PVE-induced gate length variation (σ L g,PVE ) is obtained, the PVE-induced V th fluctuation (σ V th,PVE ) is calculated by characteristics of the V th roll-off. The detailed simulation techniques for RDF and PVE simulation follow our previous works [17][18][19][20][21][22][23][24][25]. For WKF, a statistically sound Monte Carlo simulation approach is advanced, as shown in figure 1(e).…”

Section: The Statistical Simulation Techniquementioning

confidence: 99%

Simulation of characteristic variation in 16 nm gate FinFET devices due to intrinsic parameter fluctuations

Li¹,

Hwang²,

Han³

2010

Nanotechnology

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High-kappa/metal-gate and vertical channel transistors are well-known solutions to continue the device scaling. This work extensively explores the physics and mechanism of the intrinsic parameter fluctuations in nanoscale fin-type field-effect transistors by using an experimentally validated three-dimensional quantum-corrected device simulation. The dominance fluctuation sources in threshold voltage, gate capacitance and cutoff frequency have been found. The emerging fluctuation source, workfunction fluctuation, shows significant impacts on DC characteristics; however, its impact is reduced in AC characteristics due to the screening effect of the inversion layer. Additionally, the channel discrete dopant may enhance the electric field and therefore make the averaged cutoff frequency of fluctuated devices larger than the nominal value of cutoff frequency.

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“…Nevertheless, the existing random ITs at the HfO 2 /Si interface weakens the screening effect, in contrast to random dopant fluctuation (RDF). 5) For the same number of ITs, simulated device samples with similar I on but different I off may disclose the effect of random ITs' position on the off-state potential; in particular, ITs near source end alter potential barrier significantly. Large number of random ITs not only implies high density of ITs at HfO 2 /Si interface but also scatters high-field transport of inversion-layer carriers; consequently, it raises V th and impacts the on-state conducting current path, in spite of maintaining similar offstate current.…”

Section: Introductionmentioning

confidence: 99%

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

Cheng

2012

Jpn. J. Appl. Phys.

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Within the framework of the thermally activated process of the flux line or flux line bundles, and by time integration of the 1D equation of motion of the circulating current density J (ρ, t), which is suitable for thin superconducting films (R d, λ), we present numerical calculations of the current profiles, magnetization hysteresis loops and ac susceptibility χ n = χ n + iχ n for n = 1, 3 and 5 of a thin disc immersed in an axial time-dependent external magnetic field B a (t) = B dc + B ac cos(2πνt). Our calculated results are compared with those of the critical state model (CSM) and found to prove the approximate validity of the CSM below the irreversibility field. The differences between our computed results and those of the CSM are also discussed.

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Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits

Cited by 57 publications

References 59 publications

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

Simulation of characteristic variation in 16 nm gate FinFET devices due to intrinsic parameter fluctuations

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

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