RAMP: Resource-Aware Mapping for CGRAs

Dave, Shail; Balasubramanian, M.; Shrivastava, Aviral

doi:10.1109/dac.2018.8465892

Cited by 30 publications

(21 citation statements)

References 8 publications

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“…In some ventures, for instance, REGIMap [10] uses Local Register Buffers in Pes [11] (OMB). Whereas, for both LRB and OMB [12], the RAMP is only used separately. Where CGRA's buffer resources are insufficient, competitive efficiency includes the combining use of PE, Global Register Buffer (GRB), LRB and OMB.…”

Section: Literature Surveymentioning

confidence: 99%

Cgra Modulo Scheduling for Achieving Better Performance and Increased Efficiency

Phani.T¹

2021

TURCOMAT

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Coarse-Grained Reconfigurable Architectures (CGRA) is an effective solution for speeding up computer-intensive activities due to its high energy efficiency and flexibility sacrifices. The timely implementation of CGRA loops was one of the hardest problems in the analysis. Modulo scheduling (MS) was productive in order to implement loops on CGRAs. The problem remains with current MS algorithms, namely to map large and irregular circuits to CGRAs over a fair period of compilation with restricted computational and high-performance routing tools. This is mainly due to an absence of awareness of major mapping limits and a time consuming approach to solving temporary and space-related mapping using CGRA buffer tools. It aims to boost the performance and robust compilation of the CGRA modulo planning algorithm. The problem with the CGRA MS is divided into time and space and the mechanisms between the two problems have to be reorganized. We have a detailed, systematic mapping fluid that addresses the algorithms of the time mapping problem with a powerful buffer algorithm and efficient connection and calculation limitations. We create a fast-stable algorithm for spatial mapping with a retransmission and rearrangement mechanism. With higher performance and quicker build-up time, our MS algorithm can map loops to CBGRA. The results show that, given the same compilation budget, our mapping algorithm results in a better rate for compilation. The performance of this method will be increased from 5% to 14%, better than the standard CGRA mapping algorithms available.

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Section: Literature Surveymentioning

confidence: 99%

Cgra Modulo Scheduling for Achieving Better Performance and Increased Efficiency

Phani.T¹

2021

TURCOMAT

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“…Compilation time of the CGRAs is also important. In general, application mapping takes most of the compilation time, and it is completed within a few seconds to a few hours even by state-the-art mapping techniques [18]- [20]. For the multicasting, an additional compilation time in order to make the configuration data is required.…”

Section: Time To Schedule the Configuration Datamentioning

confidence: 99%

A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures

Kojima

Amano

2019

IEICE Trans. Inf. & Syst.

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A novel configuration data compression technique for coarse-grained reconfigurable architectures (CGRAs) is proposed. Reducing the size of configuration data of CGRAs shortens the reconfiguration time especially when the communication bandwidth between a CGRA and a host CPU is limited. In addition, it saves energy consumption of configuration cache and controller. The proposed technique is based on a multicast configuration technique called RoMultiC, which reduces the configuration time by multicasting the same data to multiple PEs (Processing Elements) with two bit-maps. Scheduling algorithms for an optimizing the order of multicasting have been proposed. However, the multicasting is possible only if each PE has completely the same configuration. In general, configuration data for CGRAs can be divided into some fields like machine code formats of general perpose CPUs. The proposed scheme confines a part of fields for multicasting so that the possibility of multicasting more PEs can be increased. This paper analyzes algorithms to find a configuration pattern which maximizes the number of multicasted PEs. We implemented the proposed scheme to CMA (Cool Mega Array), a straight forward CGRA as a case study. Experimental results show that the proposed method achieves 40.0% smaller configuration than a previous method for an image processing application at maximum. The exploration of the multicasted grain size reveals the effective grain size for each algorithm. Furthermore, since both a dynamic power consumption of the configuration controller and a configuration time are improved, it achieves 50.1% reduction of the energy consumption for the configuration with a negligible area overhead.

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“…Due to the difficult search in the huge space, it is unusable for all but the small DDGs. For fast compilation, most works [9]- [11], [13]- [15] integrate routing strategy exploration into the scheduling step. In BufAware mapping [9], as the first row shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…That is to say, rescheduling routing exploration is neglected in this work. Most works [10], [11], [15], as the second row shown in Fig. 2, pay more attention to rescheduling routing exploration, where routing strategy exploration is performed on those unmapped nodes from a P&R failure.…”

Section: Introductionmentioning

confidence: 99%

Routability-Enhanced Scheduling for Application Mapping on CGRAs

Zeng

Wang

2021

IEEE Access

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Coarse-Grained Reconfigurable Architectures (CGRAs) are a promising solution to domainspecific applications for their energy efficiency and flexibility. To improve performance on CGRA, modulo scheduling is commonly adopted on Data Dependence Graph (DDG) of loops by minimizing the Initiation Interval (II) between adjacent loop iterations. The mapping process usually consists of scheduling and placement-and-routing (P&R). As existing approaches don't fully and globally explore the routing strategies of the long dependencies in a DDG at the scheduling stage, the following P&R is prone to failure leading to performance loss. To this end, this paper proposes a routability-enhanced scheduling for CGRA mapping using Integer Linear Programming (ILP) formulation, where a global optimized scheduling could be found to improve the success rate of P&R. Experimental results show that our approach achieves 1.12× and 1.22× performance speedup, 28.7% and 50.2% compilation time reduction, as compared to 2 state-of-theart heuristics.INDEX TERMS Coarse-grained reconfigurable architectures (CGRAs), modulo scheduling, routing strategy, placement and routing (P&R)

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RAMP: Resource-Aware Mapping for CGRAs

Cited by 30 publications

References 8 publications

Cgra Modulo Scheduling for Achieving Better Performance and Increased Efficiency

Cgra Modulo Scheduling for Achieving Better Performance and Increased Efficiency

A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures

Routability-Enhanced Scheduling for Application Mapping on CGRAs

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