Raisin: Redundancy Analysis Algorithm Simulation

Huang, Rei-Fu; Yeh, Jen-Chieh; Li, Jin-Fu; Wu, Chenjian

doi:10.1109/mdt.2007.144

Cited by 26 publications

(10 citation statements)

References 11 publications

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“…When the detected number of faults is equal to the number of faults stored in the first test, the test is stopped to reduce test time while the test algorithm is being completed in the second serial test. The test time is greatly reduced because most of the faults are detected by the first few read operations of a March test [21]. When the post-share redundancy scheme is adopted, the number of available redundancies is always equal to or larger than the number of spares for post-bond test-repair.…”

Section: B Test-repair Flow Of 3d Memoriesmentioning

confidence: 99%

A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories

et al. 2015

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A 3-dimensional Built-In Self-Repair (3D BISR) scheme is proposed for 3-dimensional (3D) memories. The proposed 3D BISR scheme consists of two phases: a parallel test-repair phase, and a serial test-repair phase. After all memory dice are simultaneously tested, only the faulty memory dice are serially tested and repaired using one Built-In Redundancy Analysis (BIRA) module. Thus, it is a faster test-repair with low area overhead. The proposed BIRA algorithm with a post-share redundancy scheme performs exhaustive searches for all combinations of spare rows and columns. Experimental results show that the proposed 3D BISR is up to two times faster than the 3D serial test-serial repair BISR when seven 2048 2048 bit memory dice are stacked. The proposed 3D BISR requires 44.55% of the area in comparison to a 3D parallel test-parallel repair BISR for four stacked memory dice (one 128 K RAM, two 256 K RAMs, and 512 K RAM). The yield of 3D memories is the highest due to the exhaustive search BIRA algorithm with the post-share redundancy scheme as shown in various experimental results.Index Terms-3D memory, 3D built-in self-repair, area overhead, built-in redundancy analysis, built-in self-test, repair rate, yield.

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Section: B Test-repair Flow Of 3d Memoriesmentioning

confidence: 99%

A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories

et al. 2015

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“…For ease of comparison, we assume the defects only result in single-cell failures, i.e., in the failure distribution, the per centages of row, column, and cluster failures are all 0, which is the same as in [33]. Note that if row, column, and cluster failures do exist in the stacking process, then we can adopt the configurable spare scheme [18] to increase the spare flexibil ity, which is beyond the scope of this paper.…”

Section: Die Matching Algorithmmentioning

confidence: 99%

Redundancy architectures for channel-based 3D DRAM yield improvement

Lin

Chiang

et al. 2014

2014 International Test Conference

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“…When a circuit block incorporates redundancy and/or ECCs, the relationship between yield and defect density is not straightforward, and hence specialized software has been developed to analyze the yield of memories with redundancy and ECCs [34], [35]. Let's consider a simple example with just redundant word lines and single bit ECC correction on the word lines.…”

Section: B Memory Yield Modelingmentioning

confidence: 99%