Rail-to-rail fully differential sample and hold based on differential difference amplifier

Ramírez-Angulo, J.; Luján-Martínez, C.; Rubia-Marcos, C.; Carvajal, R.G.; Lopez-Martin, A.J.

doi:10.1049/el:20080996

Cited by 9 publications

(8 citation statements)

References 3 publications

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“…Reference [5] is not included as only the THA (and not the SHA) performance is available. In order to facilitate the comparison, the current work has been pre-layout simulated with no MC analysis at an input frequency of 100 kHz with a sampling rate of 1 MS/s.…”

Section: Rsha Performancementioning

confidence: 99%

“…Few SHAs capable of holding the output for a full clock cycle were proposed in the literature [2][3][4][5][6]. A true SHA samples the analog input signal during a short time and then holds the signal during almost the full clock period giving the analog-to-digital converter about twice the time to perform the conversion similar to track-and-hold amplifier (THA).…”

Section: Introductionmentioning

confidence: 99%

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A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Harb

2010

Analog Integr Circ Sig Process

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Post-layout Monte Carlo analysis and characterization as function of temperature, process, and mismatch variations of a rail-to-rail full clock fully programmable differential rectifier and sample-and-hold amplifier (RSHA) for biomedical applications are presented in this paper. The RSHA is based on a class AB fully differential two-stage operational amplifier. It uses the Miller compensation capacitor to hold the output and a duplicate of the output stage to ensure proper offset cancellation and common-mode control. The circuit is designed and implemented using a 0.35 lm CMOS technology. Results show that the total harmonic distortion, for an almost rail-to-rail input swing at 10 kHz and at 100 kS/s is equivalent to more than 9 bits in worst case. The dc output offset is below 140 lV and the error introduced by the rectification with respect to the non rectified signal is less than -100 dB. The power consumption is 3 mW with ±1.25 V supplies. The RSHA provides an output valid for more than 85% of the clock cycle.

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Section: Rsha Performancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Harb

2010

Analog Integr Circ Sig Process

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“…Utilization of Track-and-Hold circuits is another approach to alleviate slew rate requirements [3]. A common method to implement a track-and-hold circuit that solves the slew rate issue is the Miller hold capacitance method [4], [5]. It uses the op-amp as a voltage follower during the tracking phase and the Miller capacitor to hold the output during the hold phase.…”

Section: Introductionmentioning

confidence: 99%

Power Efficient Simple Technique to Convert a Reset-and-Hold Into a True-Sample-and-Hold Using an Auxiliary Output Stage

et al. 2020

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A technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp. It is based on a Miller op-amp with an auxiliary output stage that increases power dissipation by only 1.3%. The circuit is offset-compensated and has close to rail-to-rail swing. Experimental results of a test chip prototype in 130nm CMOS technology with 0.3mW power dissipation are provided, which validate the proposed technique.

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“…Few SHA capable of holding the output for a full clock cycle were proposed in the literature [2] [3] [4] [5]. During the sampling mode the input signal is "tracked" and a sample is taken at the moment the system is switched into the hold mode.…”

Section: Introductionmentioning

confidence: 99%

“…Its disadvantage is the mismatch due to the use of two signal paths. In the most recent SHA [5], the authors described a rail-to-rail THA based on one differential difference amplifier (DDA). The design can be extended to SHA by using 2 DDAs.…”

Section: Introductionmentioning

confidence: 99%

A rail-to-rail full clock fully differential rectifier and sample-and-hold amplifier

Harb

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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An almost rail-to-rail full clock fully differential rectifier and sample-and-hold amplifier is presented. It is based on a class AB fully differential two stage amplifier. It uses the miller compensation capacitor to hold the output and a duplicate of the output stage to ensure offset cancellation and proper common mode control. Simulation results, in 0.35 µm CMOS technology, show power consumption of 3 mW with ± 1.25 V supplies. The total harmonic distortion, for a differential input of ± 2.4 V pp at 10 kHz, is less than -56 dB. The error introduced by the rectification is less than -100 dB.

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Rail-to-rail fully differential sample and hold based on differential difference amplifier

Cited by 9 publications

References 3 publications

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Power Efficient Simple Technique to Convert a Reset-and-Hold Into a True-Sample-and-Hold Using an Auxiliary Output Stage

A rail-to-rail full clock fully differential rectifier and sample-and-hold amplifier

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