Radiation tolerant heterogeneous Multicore “system on chip” with built-in multichannel SpaceFibre switch for onboard data management and mass storage device: Components, short paper

Solokhina, Tatiana; Petrichkovich, Jaroslav; Glushkov, Alexander; Belyaev, Andrey K.; Menshenin, Leonid; Putrya, F.M.; Sheynin, Yuriy; Suvorova, Elena

doi:10.1109/spacewire.2016.7771638

Cited by 2 publications

(1 citation statement)

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“…DDR SDRAM (often referred to as DDR) sends information on both the positive and negative edges of the clock [24]. The DDR controller is built to provide suitable commands for SDRAM start-up, read/write access, periodic refreshing function, appropriate activation and precharge operations, and so on [25]. By sending data two times per cycle, DDR SDRAM increases the memory's bandwidth.…”

Section: Related Workmentioning

confidence: 99%

Development of SRAM-APB protocol interface and verification

Karthikeyan,

Balamurugan,

Rao Namamula

et al. 2023

Eng. Res. Express

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The purpose of this mechanism is to enhance the chip’s internal connections and read/write memory capabilities. The Advanced Microcontroller Bus Architecture (AMBA) is one such shared bus that uses static random-access memory to achieve this goal. As a result, it’s important to weigh a variety of design options before diving into the Verilog description. It’s also important to remember that the system must be designed to accommodate a large number of interoperable modules and memories. The design, on the other hand, starts with fewer modules and a less complicated description and realisation that relies on memory access. ModelSim is used to simulate after the delay has been modelled in Verilog. Since the interface’s static random-access memory uses an APB protocol, its performance may be tested at this stage. In addition, Questasim employs verification modules and System Verilog technologies to guarantee the system’s operation. From the obtained results, the Direct Memory Access (DMA) with SRAM-APB outperforms the alternatives, particularly in frame transmission schemes, with a wire efficiency that is 1.4 times higher and a dynamic energy efficiency that is nearly twice as high as those of conventional configurations.

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Section: Related Workmentioning

confidence: 99%