Radiation-Hardening-By-Design of the HighPerformance CMOS Nanometer System-on-chip

Abstract

The influence of the dominant radiation effects in bulk CMOS IC and VLSI on their electrical parameters and characteristics is analyzed. The effects of scaling and electrical modes on device and parasitic n-MOS transistors on the radiation hardness parameters are considered. The methodology of radiation-hardening-by-design of system-on-chip (SoC) and SRAM was developed for the 250-90 nm bulk CMOS processes. Technical solutions are proposed that provide an increased level of total ionizing dose tolerance, failure tolerance, and the absence of the latch-up effect. The framework for high-performance radiation-hardened SoC and SRAM design, containing standard cell libraries and IP-blocks, has been created. Basic technical solutions are certified on special test chips and as part of developed VLSI.