Radiation hardened SEU tolerant Reed Solomon encoder and decoder

Jaswal, Manpreet Kaur; Mallik, Debjyoti; Kaur, Manjit

doi:10.1109/spin.2016.7566730

Cited by 5 publications

(2 citation statements)

References 2 publications

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“…Several works have studied the protection of RS decoders against SEUs. In [11], the reset signaling, clock and flip-flops in the decoder are protected based on TMR. The authors in [12] proposed to detect faults in the RS decoder by checking the correctness and Hamming weight of the decoded codeword.…”

Section: Introductionmentioning

confidence: 99%

Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders

Gao

Shi

Liu

et al. 2023

IEEE Trans. VLSI Syst.

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Reed-Solomon erasure codes (RS-EC) are widely applied in storage and packet communication systems to recover erasures. When implemented on a Field Programmable Gate Array (FPGA) in a space platform, the RS-EC decoder will suffer Single Event Upsets (SEUs) that can cause failures. In this paper, the reliability of an RS-EC decoder implemented on an FPGA to errors on the configuration memory is firstly studied based on hardware SEU injection experiments. We found that the reliability is lower for larger number of erased symbols, but there are still about 85% SEUs can be tolerated by the decoder itself even for the maximum number of erased symbols within the recovery capability. In addition, around 10%-25% SEUs on critical bits can cause system exceptions. Based on these results, a Duplication With Comparison (DWC) scheme is proposed for the protection of the RS-EC decoder. In particular, a checksum parity based approach is proposed to detect the faulty decoder to reduce the computation overhead. Experimental results show that the reliability of the DWC protected RS-EC decoder to SEUs on the configuration memory is almost the same of a traditional Triple Modular Redundancy (TMR) protection, and the resource usage is only about 2.15× that of the unprotected decoder.Index Terms-Reed Solomon decoder erasure codes (RS-EC), Single Event Upsets (SEUs), field-programmable gate array (FPGA), Duplication with comparison (DWC), fault-tolerant.I.

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Section: Introductionmentioning

confidence: 99%

Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders

Gao

Shi

Liu

et al. 2023

IEEE Trans. VLSI Syst.

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show abstract

“…There are several works on the protection of the decoder for RS error correcting codes against SEUs. In [21], the traditional triple redundancy modular (TMR) method is applied to protect the flip-flops and the clock and reset signaling in the encoder and decoder. The authors in [22] proposed to detect faults in the RS decoder by checking whether the output is a valid codeword.…”

Section: Introductionmentioning

confidence: 99%

Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory

Gao

Zhang

Cheng

et al. 2021

IEEE Trans. VLSI Syst.

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Reed-Solomon erasure codes (RS-EC) are widely used in packet communication and storage systems to recover erasures. When the RS-EC decoder is implemented on a FieldProgrammable Gate Array (FPGA) in a space platform, it will suffer Single Event Upsets (SEUs) that can cause failures. In this paper, the reliability of an RS-EC decoder implemented on an FPGA when there are errors in the user memory is firstly studied. Then a fault detection and localization scheme is proposed based on partial re-encoding for the faults in user memory of the RS decoder. Furthermore, check bits are added in the generator matrix to improve the fault location performance. Theoretical analysis shows that the scheme could detect most faults with small missing and false detection probability. Experimental results on a case study show that more than 90% faults on user memory could be tolerated by the decoder, and the all other faults can be detected by the fault detection scheme when the number of erasures is less than the correction capability of the code. Although false alarms exist (with probability smaller than 4%), they can be used to avoid faults accumulation. Finally, the fault location scheme could accurately locate all the faults. The theoretical estimates are very close to the experiment results, which verifies the correctness of the analysis done.

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Radiation Hardened Design Based on TMR_5DFF for ASIC

Zhang

Han

et al. 2019

2019 IEEE 5th International Conference on Computer and Communications (ICCC)

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Radiation hardened SEU tolerant Reed Solomon encoder and decoder

Cited by 5 publications

References 2 publications

Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders

Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders

Design of FPGA-Implemented Reed–Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory

Radiation Hardened Design Based on TMR_5DFF for ASIC

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