Radiation Damage Estimates and Control in Ion‐Beam Lithography

Electron, ion, and x-ray lithography are all being advocated as replacements for optical lithography at some time in the future for high-volume production of integrated circuits. Of some concern is the potential for radiation damage to underlying circuit layers caused by these lithographies. In this paper we report results of an experiment designed specifically to compare damage to radiation-hardened circuits arising from the three nonoptical lithographic technologies. We employ flood exposures of metal-oxide-semiconductor (MOS) capacitors by electrons, ions, and x rays to simulate lithographic exposures. We report results of characterizations by capacitance-voltage analysis, radiation-hardness testing, and bias-stress testing. Degradation in radiation hardness is used as measure of residual damage caused by the simulated lithographic irradiations that is not annealed out at low temperatures. We find minimal damage to the oxide resulting from lithographic doses of ions. We measure voltage shifts due to oxide- and interface-trap charge introduced by x rays and electrons and find that they can be removed by standard post-metallization anneals. We find that the radiation tolerance of MOS capacitors so irradiated and annealed is nearly identical to that of devices that did not see irradiation and annealing. Moreover, in all cases, no bias-temperature instabilities resulted from the exposure-anneal sequences. We find that all three types of lithographic techniques are promising candidates for use in advanced, radiation-hardened integrated circuit technologies.

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Radiation Damage Estimates and Control in Ion‐Beam Lithography

Abstract: not Available.

Cited by 3 publications

References 5 publications

Positive Radiation Resists

Positive Radiation Resists

Radiation Exposure

Damage due to electron, ion, and x-ray lithography

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