Racetrack Memory: A high-performance, low-cost, non-volatile memory based on magnetic domain walls

Thomas, Luc; Yang, See‐Hun; Ryu, Kwang-Su; Hughes, Brian; Rettner, Charles; Wang, Ding-Shuo; Tsai, Ching-Hui; Shen, Kuei-Hung; Parkin, S. S. P.

doi:10.1109/iedm.2011.6131603

Cited by 61 publications

(29 citation statements)

References 7 publications

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“…To the best of our knowledge, there is no prior work using DWM to implement variable length FIFO queues suitable for utilization in a NoC. However, a fixed-length shift register, realized by perpendicular magnetic anisotropy (PMA) technology, has been demonstrated [4,12]. In addition to improvements which focus on emerging memories, a substantial amount of research has been performed to reduce the number and optimize the usage of network buffers.…”

Section: Background and Related Workmentioning

confidence: 98%

Domain-wall memory buffer for low-energy NoCs

Kline

Melhem

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Networks-on-chip (NoCs) have become a leading energy consumer in modern multi-core processors, with a considerable portion of this energy originating from the large number of virtual channel (FIFO) buffers. While emerging memories have been considered for many architectural components such as caches, the asymmetric access properties and relatively small size of network-FIFOs compared to the required peripheral circuitry has led to few such replacements proposed for NoCs. In this paper, we propose control schemes that leverage the "shift-register" nature of spintronic domainwall memory (DWM) to replace conventional memory buffers for the NoC. Our results indicate that the best shift-based scheme utilizes a dual-nanowire approach to ensure that reads and writes can be more effectively aligned with access ports for simultaneous access in the same cycle. Our approach provides a 2.93X speedup over a DWM buffer using a traditional FIFO memory control scheme with a 1.16X savings in energy. Compared to a SRAM-FIFO it exhibits an 8% message latency degradation versus a 56% energy reduction. The resulting approach achieves a 53% reduction in energy delay product compared to SRAM and a 42% reduction in energy delay product versus STT-MRAM.

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Section: Background and Related Workmentioning

confidence: 98%

Domain-wall memory buffer for low-energy NoCs

Kline

Melhem

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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show abstract

“…From the sum and carry logic circuit realized in [10], the non-volatile DW nanowire is found to be the most suitable device for implementing the in-memory logic of the proposed block-level architecture. DW nanowire [15], [16], [17] is itself a non-volatile leakage-free memory device as it uses spin rather than charge as the physical state variable for storing information. As will be illustrated in later section, the inherent match between the characteristics of DW nanowire and the key logic operations of AES has drastically reduced the circuit complexity.…”

Section: Proposed Dw-nanowire Based In-memory Computing Architecmentioning

confidence: 99%

“…Beyond high-density and standby-powerfree memory [13], spintronic is also a promising technology for big-data storage with logic-in-memory computing capability. Such capability was first exploited in our preliminary design of DW-AES [14] based on the emerging domain-wall (DW) nanowire [15], [16], [17], [18], [19]. In this paper, the key differentiation of block-level from cell-level in-memory computing architecture that enables the full mapping of AES operations by DW nanowire devices is elaborated for the first time.…”

Section: Introductionmentioning

confidence: 99%

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory

Wang

Chang

et al. 2016

IEEE Trans.Inform.Forensic Secur.

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Big-data storage poses significant challenges to anonymization of sensitive information against data sniffing. Not only will the encryption bandwidth be limited by the I/O traffic, the transfer of data between processor and memory will also expose the input-output mapping of intermediate computations on I/O channels that are susceptible to semi-invasive and noninvasive attacks. Limited by the simplistic cell-level logic, existing logic-in-memory computing architectures are incapable of performing the complete encryption process within the memory at reasonable throughput and energy efficiency. In this paper, a block-level in-memory architecture for Advanced Encryption Standard (AES) is proposed. The proposed technique, called DW-AES, maps all AES operations directly to the domainwall nanowires. The entire encryption process can be completed within a homogeneous, high-density and standby-power-free non-volatile spintronic based memory array without exposing the intermediate results to external I/O interface. Domain-wall nanowires based pipelining and multi-issue pipelining methods are also proposed to increase the throughput of the baseline DW-AES with insignificant area overhead and negligible difference on leakage power and energy consumption. The experimental results show that DW-AES can reduce the leakage power and area by orders of magnitude compared to existing CMOS ASIC accelerators. It has an energy efficiency of 22 pJ/bit, which is 5× and 3× better than the CMOS ASIC and memristive CMOL based implementations, respectively. Under the same area budget, the proposed DW-AES achieves 4.6× higher throughput than the latest CMOS ASIC AES with similar power consumption. The throughput improvement increases to 11× for pipelined DW-AES at the expense of doubling the power consumption.

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“…Also, the read-operation will not contribute in-cell delay. The delay of shift-operation can be calculated by (12) in which v prop is the domain-wall propagation velocity that can be calculated by Equation 7. The Joule heat caused by the injected current is calculated as the shift-operation dynamic energy.…”

Section: Domain-wall Nanowire Based Main Memorymentioning

confidence: 99%

“…For example, STT-RAM is considered as the second-generation of spin-based memory, which has sub-nanosecond magnetization switching time and sub-pJ switching energy [8], [9], [10]. As the thirdgeneration of spin-based memory, domain-wall nanowire, also known as racetrack memory [11], [12], is a newly introduced NVM device that can have multiple bits densely packed in one single nanowire, where each bit can be accessed by the manipulation of the domain-wall. Compared with STT-RAM, the domain-wall nanowire is able to provide the similar speed and power but with much higher density or throughput [13].…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices

Wang

et al. 2015

IEEE Trans. Nanotechnology

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The data-oriented applications have introduced increased demands on memory capacity and bandwidth, which raises the need to rethink the architecture of the current computing platforms. The logic-in-memory architecture is highly promising as future logic-memory integration paradigm for high throughput data-driven applications. From memory technology aspect, as one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) not only shows potential as future power efficient memory, but also computing capacity by its unique physics of spintronics. This paper explores a novel distributed in-memory computing architecture where most logic functions are executed within the memory, which significantly alleviates the bandwidth congestion issue and improves the energy efficiency. The proposed distributed in-memory computing architecture is purely built by domain-wall nanowire, i.e. both memory and logic are implemented by domain-wall nanowire devices. As a case study, neural network based image resolution enhancement algorithm, called DW-NN, is examined within the proposed architecture. We show that all operations involved in machine learning on neural network can be mapped to a logic-in-memory architecture by non-volatile domain-wall nanowire. Domain-wall nanowire based logic is customized for in machine learning within image data storage. As such, both neural network training and processing can be performed locally within the memory. The experimental results show that the domain-wall memory can reduce 92% leakage power and 16% dynamic power compared to main memory implemented by DRAM; and domainwall logic can reduce 31% both dynamic and 65% leakage power under the similar performance compared to CMOS transistor based logic. And system throughput in DW-NN is improved by 11.6x and the energy efficiency is improved by 56x when compared to conventional image processing system. 1536-125X (c)

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Racetrack Memory: A high-performance, low-cost, non-volatile memory based on magnetic domain walls

Cited by 61 publications

References 7 publications

Domain-wall memory buffer for low-energy NoCs

Domain-wall memory buffer for low-energy NoCs

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory

An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices

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