Quenching Circuit and SPAD Integrated in CMOS 65 nm with 7.8 ps FWHM Single Photon Timing Resolution

Abstract

This paper presents a new quenching circuit (QC) and single photon avalanche diode (SPAD) implemented in TSMC CMOS 65 nm technology. The QC was optimized for single photon timing resolution (SPTR) with a view to an implementation in a 3D digital SiPM. The presented QC has a timing jitter of 4 ps full width at half maximum (FWHM) and the SPAD and QC has a 7.8 ps FWHM SPTR. The QC adjustable threshold allows timing resolution optimization as well as SPAD excess voltage and rise time characterization. The adjustable threshold, hold-off and recharge are essential to optimize the performances of each SPAD. This paper also provides a better understanding of the different contributions to the SPTR. A study of the contribution of the SPAD excess voltage variation combined to the QC time propagation delay variation is presented. The proposed SPAD and QC eliminates the SPAD excess voltage contribution to the SPTR for excess voltage higher than 1 V due to its fixed time propagation delay.

3D Photon-To-Digital Converter for Radiation Instrumentation: Motivation and Future Works

“…This allows extremely low SPTR (<20 ps FWHM), as first demonstrated with a planar SPAD in a custom process [ 124 ]. FSI SPADs made in standard CMOS technologies can also reach ultimate timing resolution (<10 ps FWHM), at the cost of high-noise and low PDE [ 125 ].…”

“…For the quenching and recharge branch, multiple architectures are present in the literature: traditional passive, active or mixed (passive quenching–active recharge, variable load quenching, etc.) [ 22 , 32 , 67 , 91 , 125 , 134 ]. The main challenges for the quenching and recharge branch are to allow for a maximum SPAD excess voltage for the PDE while minimize the capacitance on the node for the timing and noise.…”

“…To reduce the timing jitter, the capacitance at the node of the detector should be minimized to increase the slope of the signal. A mixed architecture such as passive quenching–active recharge or a variable load quenching allows for minimization of the capacitance directly connected to the SPAD, as compared to a full active quenching circuit, by reducing the number of required transistors at the reading node [ 125 ]. On the other hand, to reduce correlated noise and power consumption, both minimizing the capacitance and stopping the avalanche before the complete discharge of the SPAD limits the number of carriers involved [ 67 ].…”

“…In a 3D architecture, more real estate is available and a comparator with an adjustable threshold can be implemented to obtain a better SPTR [ 137 ]. One of the contributions to the timing jitter is given by the ratio of the signal noise over the slope of the signal at the discrimination point [ 125 ]. Being able to set the threshold at the optimal value is the advantage of a comparator-based architecture over the inverter.…”

“…In [ 137 ], they report that excellent SPTR (35 FWHM) can be obtained if the avalanche is detected at low levels while the multiplication process is still confined to the photoelectric interaction point. Following that, multiple SPAD-QC pairs with a comparator were developed to reach an SPTR of 27 FWHM [ 32 ], 20 FWHM [ 138 , 139 ] and finally FWHM [ 125 ]. The adjustable threshold is also handy for characterization purposes: scanning the threshold over the input dynamic range provides information on SPAD voltage breakdown variations and the risetime of the SPAD signal [ 125 , 140 ].…”