Qubit Test Synthesis Processor for SoC Logic

Gharibi, Wajeb; Devadze, David; Hahanov, Vladimir; Litvinova, Eugenia; Hahanov, Ivan

doi:10.1109/ewdts.2019.8884476

Cited by 9 publications

(16 citation statements)

References 13 publications

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“…ii) The algorithms for modeling and simulating sequential circuits are associated with an unpredictable number of iterations [11]. iii) A significant amount of data structures for the analysis of digital systems-on-chips negatively affects the performance of fault simulation methods and test synthesis [15]- [22]. iv) Fault simulation algorithms for highdimensional logic or the analysis of circuits with converging branches are complex [10].…”

Section: Introductionmentioning

confidence: 99%

Vector-logic computing for faults-as-address deductive simulation

Gharibi

Hahanov

Chumachenko

et al. 2023

IJRA

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The aim of the research is to create logic-free vector computing, leveraging read-write transactions in memory, to solve the problems of modeling and simulation stuck-at-fault combinations for complex logic elements and digital structures. At the same time, the problem of creating smart data structures based on logical vectors, truth tables, and deductive matrices is considered to simplify algorithms for parallel stuck-at-fault simulation. Vector computing is a computational process based on read-write transactions on bits of a binary vector of functionality, where the input data and faults are the addresses of the bits. A method for the synthesis of deductive vectors for propagating input fault lists is proposed, which has a quadratic computational complexity of read-write transactions. Deductive vectors, combined into a quadratic matrix, represent explicit data structures for parallel simulation of single and multiple stuck-at-faults. The initial information for constructing a deductive matrix is a logical vector and a bit-recoding matrix. Matrix is easily obtained using a recursive procedure based on the combinatorial properties of the truth table. Considering emerging trends, focused on in-memory computing, an algorithm for fault, as addresses, simulation is proposed, using logical and deductive vectors placed in memory. The simulation algorithm is proposed not to use commands of powerful processors.

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Section: Introductionmentioning

confidence: 99%

Vector-logic computing for faults-as-address deductive simulation

Gharibi

Hahanov

Chumachenko

et al. 2023

IJRA

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“…In this case, the matrix (table) and the vector are two forms for describing models that pass into each other. A vector (binary, multi-valued) is a compact form of a truth table in the form of an ordered sequence of output states, if the input address components are sorted in ascending order [7][8][9][10][11][12][13]. The matrix, if necessary, expands into a one-dimensional vector for the convenience of parallel data processing in register memory.…”

mentioning

confidence: 99%

“…• A significant amount of data structures for the analysis of digital systems-on-chips, which negatively affects the performance of fault simulation methods and test synthesis [1,3,6,9,[16][17][18][19].…”

mentioning

confidence: 99%

“…The essence of deductive simulation is to change the logic of the element F depending on the input conditions T. Deductive modeling, proposed exactly 50 years ago by Armstrong [26], is still the most elegant and effective tool for analyzing the quality of tests and synthesizing tables for detecting faults, tracing the propagation paths of the fault. Further, its implementation is proposed based on the vector form of logic description [7][8][9][10][11][12][13], which excludes logical analytical forms. This makes it possible to significantly simplify the algorithms for the synthesis of deductive models and their application for interpretative simulation of digital elements and large-scale circuits.…”

mentioning

confidence: 99%

“…To compare the computational complexity of obtaining deductive formulas, the analytical classical procedure for analyzing the or-element is given below. It operates by Boolean equations, for which complex solvers are required [9,12,13]:…”

mentioning

confidence: 99%

See 2 more Smart Citations

Vector-deductive Memory-based Transactions for Fault-as-address Simulation

Gharibi¹,

Hahanova²,

Hahanov³

et al. 2023

Èlektron. model.

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The main idea is to create logic-free vector computing, using only read-write transactions on address memory. The strategic goal is to create a deterministic vector-quantum computing using photons for read-write transactions on stable subatomic memory elements. The main task is to implement new vector computing models and methods based on primitive read-write transactions in vector flexible interpretive fault modeling and simulation technology, where data is used as addresses for processing the data itself. The essence of vector computing is read-write transactions on vector data structures in address memory. Vector computing is a computational process based on elementary read-write transactions over cells of binary vectors that are stored in address memory and form a functionality where the input data to be processed is the addresses of these cells. The advantages of a vector universal model for a compact description of ordered processes, phenomena, functions, and structures are defined for the purpose of their parallel analysis. Analytical expressions of logic, which require algorithmically complex calculators, are replaced by output state vectors of elements and digital circuits, focused on the parallelism of register logical procedures on regular data structures. A vector-deductive method for formula synthesis for propagating input lists (data) of faults is proposed, which has a quadratic computational complexity of register operations. A new matrix of deductive vectors has been synthesized, which is characterized by the following properties: compactness, parallel data processing based on a single read-write transaction in memory, elimination of traditional logic from fault simulation procedures, full automation of its synthesis process, and focus on technological solving all problems of technical diagnosis. In the work, the transition to vector logic in the organization of computing and the elimination of traditional logic presented in the form of tables and analytical expressions were carried out. The use of read-write transactions on memory in the absence of a command system focuses the new vector-logic computing towards deterministic quantum architectures based on stable subatomic memory particles.

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