Qubit compatible superconducting interconnects

Abstract

We present a fabrication process for fully superconducting interconnects compatible with superconducting qubit technology. These interconnects allow for the three dimensional integration of quantum circuits without introducing lossy amorphous dielectrics. They are composed of indium bumps several microns tall separated from an aluminum base layer by titanium nitride which serves as a diffusion barrier. We measure the whole structure to be superconducting (transition temperature of 1.1 K), limited by the aluminum. These interconnects have an average critical current of 26.8 mA, and mechanical shear and thermal cycle testing indicate that these devices are mechanically robust. Our process provides a method that reliably yields superconducting interconnects suitable for use with superconducting qubits.

High coherence superconducting microwave cavities with indium bump bonding

“…Finally, it is compatible with standard lithographic techniques, enabling the adaptation of existing approaches for scaling up quantum circuits. Recently, indium bonding has been used for chip hybridization and interconnections [8,[14][15][16]. In this work, we optimize the existing bonding technique to attain ultra-low loss joints in the microwave frequency range.…”

Advantages of a modular high-level quantum programming framework

“…For example, it is possible to build superconducting qubits on a linear nearest neighbor chain because this allows to use a two dimensional chip design with control lines coming from the sides. A technologically more advanced design is to have the control lines coming from the third dimension and hence allowing qubits to be connected on a nearest neighbor square grid [40]. While for small experiments with tens of gates and only a few qubits the mapping process could be optimized manually, this will no longer be the case for hardware with more than 50 qubits especially as early devices might have irregular graphs due to faulty qubits.…”

Solid-state qubits integrated with superconducting through-silicon vias

“…Addressing the interior elements of a large two-dimensional (2D) array requires moving out of a planar geometry to route wires past the outer elements of the array. In the short-and mediumterm, accessing the interior of a qubit array can be achieved with a single extra metallization layer (i.e., air bridges and standard flipchip bonding) or by a single layer of vertical I/O (i.e., pin-chips, pogo pins, and similar technologies) [9][10][11][12][13][14][15][16] . However, larger and more complex quantum system architectures may need to utilize multiple levels of qubits and complex signal routing, which necessitates the development of multilayer control and routing capabilities.…”