Quaternary logic circuits in 2- mu m CMOS technology

Abstract

Novel quaternary logic circuits, designed in 2-u.m'CMOS technology, are presented. These include threshold detector circuits with an improved output voltage swing and a simple binary-to-quaternary encoder circuit. Based on these, the literal circuits, the quaternary-tobinary decoder, and the quaternary register designs are derived. A novel scheme for improving the power-delay product of pseudo-NMOS circuits is developed. Simulations for an inverter indicate a 66% improvement over a conventional pseudo-NMOS circuit. Noise-margin and tolerance estimations are made for the threshold detectors. To demonstrate the utility of these circuits, a quaternary sequential/storage logic array (QSLA), based on the Allen-Givone algebra, has been designed and fabricated. The prototype chip occupies an area of 4.84 mm 2 , is timed with a 2.2-MHz clock, and consumes 93 mW of power.

CMOS quaternary logic encoder-decoder circuits

“…Therefore, it will be necessary to provide encoding and decoding circuitry to perform the required conversion between MVL signalling on the bus and the binary processing circuits. (Brilman et al 1983, Mangin and Current 1986, Rattus et al 1990, Shanbhag et al 1990). …”

Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs

“…Several methods have been proposed for binary to quaternary and vice versa converters [14,15,16,17].…”

Logical Design of Quaternary Signed Digit Conversion Circuit and its Effectuation using Operational Amplifier

“…Park et al [20] designed quaternary logic circuit using υ MOS where 0.5V, 1.5V, 2.5V and 3V. Logic levels in Shanbhag et al are 0V, 2V, 4V and 6V respectively [13]. Tanable et al [23] designed redundant MVL circuit using CMOS where they use binary two states 0-0, 0-1, 1-0 and 1-1 as quaternary 0, 1, 2 and 3 states respectively.…”

“…Ordinary quaternary number can be easily expressed as two bit binary number [10][11][12][13][14][15]. The implementation of multi- valued logic using ordinary quaternary digit has been studied by using various devices, such as I 2 L [16], CCD [10,17], CMOS [11,[13][14]18], ECL [12,19], υ MOS [20], MESFET [21] in electronics.…”

“…The implementation of multi- valued logic using ordinary quaternary digit has been studied by using various devices, such as I 2 L [16], CCD [10,17], CMOS [11,[13][14]18], ECL [12,19], υ MOS [20], MESFET [21] in electronics. In these literatures many logic levels had been considered.…”