Quantum Foundations of Classical Reversible Computing

Abstract

The reversible computation paradigm aims to provide a new foundation for general classical digital computing that is capable of circumventing the thermodynamic limits to the energy efficiency of the conventional, non-reversible paradigm. However, to date, the essential rationale for and analysis of classical reversible computing (RC) has not yet been expressed in terms that leverage the modern formal methods of non-equilibrium quantum thermodynamics (NEQT). In this paper, we begin developing an NEQT-based foundation for the physics of reversible computing. We use the framework of Gorini-Kossakowski-Sudarshan-Lindblad dynamics (a.k.a. Lindbladians) with multiple asymptotic states, incorporating recent results from resource theory, full counting statistics, and stochastic thermodynamics. Important conclusions include that, as expected: (1) Landauer's Principle indeed sets a strict lower bound on entropy generation in traditional non-reversible architectures for deterministic computing machines when we account for the loss of correlations; and (2) implementations of the alternative reversible computation paradigm can potentially avoid such losses, and thereby circumvent the Landauer limit, potentially allowing the efficiency of future digital computing technologies to continue improving indefinitely. We also outline a research plan for identifying the fundamental minimum energy dissipation of reversible computing machines as a function of speed.

Logical and Physical Reversibility of Conservative Skyrmion Logic

“…The conventional non-reversible paradigm for general digital computing will eventually approach fundamental thermodynamic limits on its energy efficiency, which stem ultimately from the fact that this standard paradigm relies primarily on operations that systematically discard correlated logical information, and therefore increase entropy ( [1], [2], [3]). For example, a typical digital logic architecture in CMOS destructively overwrites the output of each active logic gate with a new bit value on each clock cycle.…”