Quantum dots with split enhancement gate tunnel barrier control

Abstract

We introduce a silicon metal-oxide-semiconductor quantum dot architecture based on a single polysilicon gate stack. The elementary structure consists of two enhancement gates separated spatially by a gap, one gate forming a reservoir and the other a quantum dot. We demonstrate, in three devices based on two different versions of this elementary structure, that a wide range of tunnel rates is attainable while maintaining single-electron occupation. A characteristic change in slope of the charge transitions as a function of the reservoir gate voltage, attributed to screening from charges in the reservoir, is observed in all devices, and is expected to play a role in the sizable tuning orthogonality of the split enhancement gate structure. The all-silicon process is expected to minimize strain gradients from electrode thermal mismatch, while the single gate layer should avoid issues related to overlayers (e.g., additional dielectric charge noise) and help improve yield. Finally, reservoir gate control of the tunnel barrier has implications for initialization, manipulation and readout schemes in multi-quantum dot architectures.Silicon (Si) quantum dots (QDs) are strong contenders for the realization of spin qubits. 1,2 Silicon germanium heterostructure (Si/SiGe) platforms with integrated micromagnets 3 have produced the highest performance qubits, 4-6 with fidelities over 99.9%, 7 while metal-oxidesemiconductor (MOS) platforms have also achieved fault tolerant fidelities. 8 Most of the high performance systems mentioned above are enhancement mode devices comprising at least two layers of control gates. The overlapping gates ensure strong confinement and the highest electrostatic control over regions surrounding the QDs. These current multi-stack devices have therefore achieved excellent tunability, thanks in part to an independant control of reservoirs, dots and tunnel barriers through respectively dedicated gates. On the other hand, single-layer enhancement mode devices are being explored for ease of fabrication and potentially higher yield, in both Si/SiGe and MOS systems. [9][10][11][12][13] In particular, all-silicon MOS single-layer devices are expected to avoid thermal mismatch and additional dielectric charge noise from overlayers. 14,15 These single-layer devices generally use a single gate to form a source-dot-drain channel, relying on constrictions and lateral depletion gates to shape the confinement potential. 9,16 Reservoir filling, dot charge occupation and tunnel rates are therefore controlled differently than in multi-gate stack architectures. Various architectures and methods of tunnel barrier control impact tunability differently, and understanding those differences will influence choices of multi-QDs initialization, manipulation and readout schemes, including automatic tuning procedures, 17,18 as well as reproducibility, versatility and scalability of devices. 19 Here we explore a single gate stack structure featuring a split gate for dot and reservoir formation. The tunnel barrier is a) S. Rochet...

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