Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

Tangudu, Jawaharlal; Gunturi, Sarma; Jalan, Saket; Janardhanan, Jayawardan; Ganesan, Raghu; Sahu, Debapriya; Waheed, K.; Wallberg, J.; Staszewski, Robert Bogdan

doi:10.1109/iscas.2009.5117932

Cited by 20 publications

(5 citation statements)

References 6 publications

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“…The power consumption reduction level of the improved counting mode is shown in Figure 8. The power consumption reduction level Pr is: (5) where Pi represents the power consumption of the improved TDC, and Ptr represents the power consumption of the traditional structure.…”

Section: Modeling Analysismentioning

confidence: 99%

“…There are many architectures for high resolution TDC, including a vernier based delay chain TDC[1], a time-amplifier based TDC [2,3], and a gated ring oscillator (GRO) TDC [4]. Pure digital TDC based on a delay chain has the advantages of high throughput and simple structure [5], therefore, it is increasingly appearing in various applications.…”

Section: Introductionmentioning

confidence: 99%

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A Time-to-Digital Converter for Reducing Redundant Counting of SS ADC in High-Speed CmCMOS os Image Sensor

Li,

Gao

2024

Preprint

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To reduce the redundant counting of TDC in high-speed applications and thus reduce power consumption, a TDC architecture is proposed to quantify the difference between two adjacent rows of pixel signals. This structure can remove the identical part between two rows of pixel signals by adjusting the start and stop signal of the TDC, which will reduce the number of flipping of D flip-flops in the TDC. In the 110nm CMOS process, simulation results show that this design achieves an effective number of bits (ENOB) of 4.72 bits and a Figure of Merit (FoM) of 104.7 fJ/step - 162.3 fJ/step with a power consumption ranging from 60 µW to 93 µW. Compared with traditional counting methods, the proposed TDC can reduce counting power consumption by 30%.

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Section: Modeling Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Time-to-Digital Converter for Reducing Redundant Counting of SS ADC in High-Speed CmCMOS os Image Sensor

Li,

Gao

2024

Preprint

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“…Consequently, the reported techniques attempt to improve the TDC resolution and include: TDC with fractional resolution [14], noise-shaped TDC [15], TDC with precise calibration and mismatch correction as well as clock doubler [16], TDC with time amplification [17], and TDC with doubling the resolution through additional row of flip-flop registers operating on a delayed clock [18].…”

Section: Wide Bandwidth Adpllmentioning

confidence: 99%

State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS

Staszewski

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL and offers a few novel techniques to further improve area, current consumption, testability and reliability of frequency synthesizers.978-1-4244-5309-2/10/$26.00 ©2010 IEEE

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“…There are many architectures for high-resolution TDCs, including a vernier-based delay chain TDC [5], a time amplifier-based TDC [6,7], and a gated-ring oscillator (GRO) TDC [8]. A purely digital TDC based on a delay chain offers high throughput and a straightforward structure [9], making it a popular choice with diverse applications.…”

Section: Introductionmentioning

confidence: 99%

A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor

Li,

Gao

2024

Micromachines

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To reduce the power consumption of a TDC in high-speed applications, a TDC architecture applied to SS ADC is proposed to reduce redundant counting. This structure can remove the identical part between two rows of pixel signals in a CMOS image sensor by adjusting the start and stop signal of the TDC, which will reduce the number of flipping of D flip-flops in the TDC. This structure requires the simultaneous readout of two rows of pixels in the high-speed CMOS image sensor. In the 110 nm CMOS process, simulation results show that the designed 5-bit TDC achieves an effective number of bits (ENOB) at 4.72 bits and a figure-of-merit (FOM) at 104.7–162.3 fJ/step, with a power consumption ranging from 60 µW to 93 µW. Compared with traditional counting methods, the proposed TDC can reduce counting power consumption by 30%.

show abstract

Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

Cited by 20 publications

References 6 publications

A Time-to-Digital Converter for Reducing Redundant Counting of SS ADC in High-Speed CmCMOS os Image Sensor

A Time-to-Digital Converter for Reducing Redundant Counting of SS ADC in High-Speed CmCMOS os Image Sensor

State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS

A Time-to-Digital Converter for Low-Power Consumption Single Slope Analog-to-Digital Converters in a High-Speed CMOS Image Sensor

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