Quantization analysis and enhancement of a VLSI gradient-based motion estimation architecture

Botella, Guillermo; Meyer-Baese, Uwe; García, Antonio; Rodríguez, Manuel Martín

doi:10.1016/j.dsp.2012.05.013

Cited by 48 publications

(23 citation statements)

References 20 publications

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“…[37] and multi-cycle custom instruction regarding Nios II / e. Also is shown the enhancement regarding baseline. [4,5], [9,12] .stack(SDRAM) .text(SDRAM ) [2,3] [37] and multi-cycle custom instruction regarding Nios II / f. Also is shown the enhancement regarding baseline. Fig.…”

Section: Final Results: Custom Instructions and Memory Choicementioning

confidence: 99%

“…The baseline case, design 1, is constructed using just SDRAM in every single configuration parameter of the memory system design. [1], [4,5], [9,12] .4ndc(SDRAM) text(SDRAM) [2,3] Nios II /e + CI Combinational J [1], [4,5], [9,12] .stadc(SDRAM) .text(SDRAM) [2,3] .stack(SDRAM) .text(On -chip) [6,8] …”

Section: Memory System Designmentioning

confidence: 99%

“…There are many algorithms and systems that are specifically aimed at handling multimedia task such as motion compensation and coding, which are widely used in the video coding standards. Furthermore, motion estimation is still the focus of much research, and there exist several structures and implementations using FPGAs [1][2][3][4][5][6], GPUs [7][8] and embedded systems [9] in the framework of Real-Time implementation such as surveillance, tracking, navigation and automotive applications [10][11].…”

Section: Introductionmentioning

confidence: 99%

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Customized Nios II multi-cycle instructions to accelerate block-matching techniques

et al. 2015

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This study focuses on accelerating the optimization of motion estimation algorithms, which are widely used in video coding standards, by using both the paradigm based on Altera Custom Instructions as well as the efficient combination of SDRAM and On-Chip memory of Nios II processor. Firstly, a complete code profiling is carried out before the optimization in order to detect time leaking affecting the motion compensation algorithms. Then, a multi-cycle Custom Instruction which will be added to the specific embedded design is implemented. The approach deployed is based on optimizing SOC performance by using an efficient combination of On-Chip memory and SDRAM with regards to the reset vector, exception vector, stack, heap, read/write data (.rwdata), read only data (.rodata), and program text (.text) in the design. Furthermore, this approach aims to enhance the said algorithms by incorporating Custom Instructions in the Nios II ISA. Finally, the efficient combination of both methods is then developed to build the final embedded system. The present contribution thus facilitates motion coding for low-cost Soft-Core microprocessors, particularly the RISC architecture of Nios II implemented in FPGA. It enables us to construct an SOC which processes 50×50 @ 180 fps.

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Section: Final Results: Custom Instructions and Memory Choicementioning

confidence: 99%

Section: Memory System Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Customized Nios II multi-cycle instructions to accelerate block-matching techniques

et al. 2015

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“…The FPGA technology provides the signal processing engineers with the ability to construct a custom data path that is tailored to the application at hand [26,27]. FPGAs offer the flexibility of instruction set digital signal processors, while providing the processing power and flexibility of an ASIC, and enable significant design cycle compression and time-to-market advantages, an important consideration in an economic climate with ever-decreasing market windows and short product life cycles [28,29].…”

Section: Introductionmentioning

confidence: 99%

Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

Jimenez

Meyer-Baese

Dolecek

2017

EURASIP J. Adv. Signal Process.

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New theoretical lower bounds for the number of operators needed in fixed-point constant multiplication blocks are presented. The multipliers are constructed with the shift-and-add approach, where every arithmetic operation is pipelined, and with the generalization that n-input pipelined additions/subtractions are allowed, along with pure pipelining registers. These lower bounds, tighter than the state-of-the-art theoretical limits, are particularly useful in early design stages for a quick assessment in the hardware utilization of low-cost constant multiplication blocks implemented in the newest families of field programmable gate array (FPGA) integrated circuits.

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“…The final aim of optical flow estimation is to compute an approximation to the motion field from timevarying image intensity. Several different real-time approaches to motion estimation have been proposed [1][2][3][4][5][6][7][8][9], and these could preliminarily be classified as belonging to matching domain approximations [10], energy models [11] and gradient models [12,13]. Despite the number of different models and algorithms [14], none of them covers all the problems associated with real-world processing, such as noise, illumination changes, second order motion, occlusions, etc.…”

Section: Introductionmentioning

confidence: 99%

Real-time motion estimation for image and video processing applications

Botella

Garcı́a

2014

J Real-Time Image Proc

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This contribution focuses on different topics that are covered by the special issue titled ''Real-Time Motion Estimation for image and video processing applications'' and which incorporate GPUS, FPGAs, VLSI systems, DSPs, and Multicores, among other platforms. The guest editors have solicited original contributions, which address a wide range of theoretical and practical issues related to high-performance motion estimation image processing including, but not limited to: real-time matching motion estimation systems, real-time energy-based motion estimation systems, gradient-based motion estimation systems, optical flow estimation systems, color motion estimation systems, multi-scale motion estimation systems, optical flow and motion estimation systems, analysis or comparison of specialized architectures for motion estimation systems and realworld applications.

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Quantization analysis and enhancement of a VLSI gradient-based motion estimation architecture

Cited by 48 publications

References 20 publications

Customized Nios II multi-cycle instructions to accelerate block-matching techniques

Customized Nios II multi-cycle instructions to accelerate block-matching techniques

Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

Real-time motion estimation for image and video processing applications

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