Quantitative evaluation of soft error injection techniques for robust system design

Cho, Hyungmin; Mirkhani, Shahrzad; Cher, Chen-Yong; Abraham, Jacob A.; Mitra, Subhasish

doi:10.1145/2463209.2488859

Cited by 193 publications

(90 citation statements)

References 22 publications

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“…One must differentiate those that inject faults on the data-path (flip-flops, gates) [2,3] versus those that target upsets in the CRAM of FPGAs [1,4,5,6].…”

Section: State Of the Artmentioning

confidence: 99%

“…The programs were modified to signal their completion and results checking was performed by reading back the RAM contents and comparing it with known good data. The result of each fault injection test was classified into one of four categories, based on a subset of the categories in [6]. If the results are correct at the normal completion time of the program, the fault injection is labeled as 'On Time Correct'.…”

Section: Hardware Emulation Platformmentioning

confidence: 99%

“…If it finishes late (> 1:2Â normal time) with wrong results, the fault injection is also labeled as 'Wrong Result'. Unlike the LEON3 processor used in [6], fault detection through traps or exceptions do not exist in the 8051 micro-controller, thus the corresponding category in [6] is not considered in this work.…”

Section: Hardware Emulation Platformmentioning

confidence: 99%

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New insights into the impact of SEUs in FPGA CRAMs

Sheng

Evans²,

Wen

et al. 2015

IEICE Electron. Express

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This paper presents a detailed study of the impact of SEUs in the configuration RAM (CRAM) of SRAM based FPGAs. Since modern SRAM based FPGAs support scrubbing of the CRAM, a new, intermittent CRAM SEU fault model is presented. This fault model is implemented both in simulation and on an emulation platform for an embedded processor design. The criticality of CRAM bits is studied based on their logic function, the duration of the SEU, and the workload running on the processor. These results provide new insight into the overall effectiveness of CRAM scrubbing mechanisms.

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“…One must differentiate those that inject faults on the data-path (flip-flops, gates) [2,3] versus those that target upsets in the CRAM of FPGAs [1,4,5,6].…”

Section: State Of the Artmentioning

confidence: 99%

Section: Hardware Emulation Platformmentioning

confidence: 99%

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New insights into the impact of SEUs in FPGA CRAMs

Sheng

Evans²,

Wen

et al. 2015

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…voltage- The multi-bit error injection models were primarily inspired by SEMU physical trend data, as shown in Figure 4.12 (quoted from [66]). Also, recent statistical fault injection based analysis by Cho et al [15] shows that random single bit-flips at the latch level (corresponding to an SEU) may not result in just a single bit-flip corruption at the architectural register state. Also, critical control registers outside the programmer-visible architectural state could get corrupted.…”

Section: Discussion Of Characterization Resultsmentioning

confidence: 99%

“…Also, recent statistical fault injection based analysis by Cho et al [15] shows that random single bit-flips at the latch level (corresponding to an SEU) may not result in just a single bit-flip corruption at the architectural register state. Regarding to these impacts on architectural states, AFI supports different multiple bit error injection models.…”

Section: Case Ii: Multiple Bit Errorsmentioning

confidence: 99%

First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems

Wang¹

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As the semiconductor industry keeps evolving at the pace predicted by Moore's Law, computer system architects are facing increasing challenges from the three major design constraints: performance, power, and reliability. Thermal constraints from a reasonable cooling cost do not scale well as technology evolves. The dwindling scaling on threshold voltage leads to a slower pace of supply voltage scaling. These two effects lead to an increasing power density in current and future technology generations. Reliability has emerged as a primary design constraint due to the smaller feature size and generally lower supply voltage for electronic devices. Transient errors caused by high-energy particle strike and voltage noises are expected to increase significantly in frequency.Performance improvement becomes more challenging for future architectures with limitations set by the power and the resilience constraints.Integration of accelerators to create heterogeneous processors is becoming more common for both power and performance reasons. However, this adds one more dimension to the design space that is already complex due to technology variants, system organizations, application's variability, and so on. Therefore, high-level models are essential for system designers to explore the design space and make decisions in a timely manner. Additionally, the three design constraints compete with each other. For example, resilience-aware techniques, such as DMR and TMR, are expensive in terms of power and performance, low-power designs usually come with a price of lower speed.Consequently, it requires system designers to make trade-offs by considering all the three design constraints at the same time.To address these challenges, we (1) propose an analytical modeling framework called Lumos that is capable of modeling power and performance for heterogeneous architectures with hardware iv v accelerators. Then we (2) use Lumos to explore the design space composed of CPU cores and accelerators, revealing important scaling trend for future heterogeneous architectures. We further (3) propose a rapid modeling framework to characterize resilience across a range of applications in DSP, and image processing domains; And finally we (4) propose an integrated framework to optimize energy-efficiency by trading off design constraints of power, performance and resilience. Acknowledgments

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Cross-Layer Resilience Against Soft Errors: Key Insights

Mueller-Gritschneder

Cheng

Sharif

et al. 2020

Dependable Embedded Systems

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Driven by technology scaling, integrated systems become more susceptible to various causes of random hardware faults such as radiation-induced soft errors. Such soft errors may cause malfunction of the system due to corruption of data or control flow, which may lead to unacceptable risks for life or property in safety-critical applications. Hence, safety-critical systems deploy protection techniques such as hardening and redundancy at different layers of the system stack (circuit, logic, architecture, OS/schedule, compiler, software, algorithm) to improve resiliency against soft errors. Here, cross-layer resilience techniques aim at finding lower cost solutions by providing accurate estimation of soft error resilience combined with a systematic exploration of protection techniques that work collaboratively across the system stack. This chapter demonstrates how to apply the cross-layer resilience principle on custom processors, fixed-hardware processors, accelerators, and SRAM memories (with a focus on soft errors) and presents key insights obtained.

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Quantitative evaluation of soft error injection techniques for robust system design

Cited by 193 publications

References 22 publications

New insights into the impact of SEUs in FPGA CRAMs

New insights into the impact of SEUs in FPGA CRAMs

First-Order Modeling Frameworks for Power-Efficient and Reliable Multiprocessor Systems

Cross-Layer Resilience Against Soft Errors: Key Insights

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