Quantitative analysis of multilayer switching networks providing multiple internal routes

Abstract

Constructing capable and scalable parallel computers or connecting contemporary networks efficiently makes multistage switching networks essential and significant devices. This is why they remain an interesting field of research and are being continually improved. This paper introduces a new idea-a new architecture-to ameliorate the behaviour of the networks' connection points.The proposed novel construction accommodates multiple internal paths and a fan-out at the end. Via this study, basic features of this introduced fabric (such as cost, reliability, and performance measures) are presented in a quantitative manner. Moreover, some comparisons-especially in terms of complexity, cost, and reliability-with other similar modern constructions that also enclose multiple internal routes are shown. This study reveals that the proposed multistage system improves performance metrics, fault tolerance, and reliability and indicates that due to its properties, this innovative device can be used in the commercial sector. KEYWORDS multistage architecture, multilayer multistage interconnection networks, performance evaluation, quantitative analysis, reliability Int J Commun Syst. 2018;31:e3785.wileyonlinelibrary.com/journal/dac

A Primer on Design Aspects and Recent Advances in Shuffle Exchange Multistage Interconnection Networks

“…Prior surveys have contributed to our understanding of MINs, however, a closer look into prior art in this area reveals that several issues relating to the design aspects of MINs are scattered in the literature. Furthermore, new developments on the design, analysis and evaluation of MINs (such as [1,6,[20][21][22][23][24][25][26][27][28][29]) have emerged within the past few years. Specifically, new ways of enhancing the reliability and fault tolerance of MINs have been proposed in some of these works while others have provided insightful performance evaluations that increase our understanding of these networks.…”

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“…Stergiou and Garofalakis [21] proposed an interconnect architecture that accommodates several internal paths and a fan-out at the end. Particularly, the authors combined both the multipath and multilayer-based architectures to yield a network of size N × N with a total of (log k N − S) stages (S refers to the number of stages of a segment with a single layer) and 3N 4 switches in each stage.…”

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