Quantifying the Performance Impact of Memory Latency and Bandwidth for Big Data Workloads

Clapp, Russell M.; Dimitrov, Martin; Kumar, Karthik; Viswanathan, Vish; Willhalm, Thomas

doi:10.1109/iiswc.2015.32

Cited by 28 publications

(21 citation statements)

References 20 publications

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“…of Clapp et al [4], our study shows that the relationship between bandwidth and latency cannot be approximated with a single curve. To the best of our knowledge, ours is the first study of memory system read latency that makes this conclusion.…”

Section: Memory System Profilingcontrasting

confidence: 49%

“…2 Increasing the proportion of write requests therefore reduces the sustainable bandwidth and increases the loaded latency. Recently, Clapp et al [4] also did a preliminary analysis of bandwidth-latency curves for different memory frequencies (DDR3-1333 and DDR3-1600) and different read-to-write ratios (3:1 and 2:1). Based on an analysis of four curves, the authors conclude that it is sufficient to use a single, generic memory bandwidth-latency curve for different frequencies and memory traffic compositions.…”

Section: Memory System Profilingmentioning

confidence: 99%

“…This section derives the relationship between latency and performance for a simple in-order CPU. In the interest of helping the reader to follow the formulas, we start by summarizing PROFET's inputs and outputs in We start by partitioning the application cycles-per-instruction, CPI tot , into two components [4,8,14,22]: CPI tot = CPI 0 + CPI LLC . The first component, CPI 0 , is the application's CPI for the hypothetical case of a 100% LLC hit rate.…”

Section: In-order Processorsmentioning

confidence: 99%

“…Computation of the CPI component that corresponds to the execution stalls due to the LLC misses (Eq. 1) is described by previous studies [3,4,14]. Hennessy and Patterson [14] and Karkhanis and Smith [22] also analyze execution of independent instructions Ins ooo after the LLC miss (Eq.…”

Section: Novelties Of the Presented Analytical Modelmentioning

confidence: 99%

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Profet

Radulovic

Verdejo

Carpenter

et al. 2019

Proc. ACM Meas. Anal. Comput. Syst.

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The approaching end of DRAM scaling and expansion of emerging memory technologies is motivating a lot of research in future memory systems. Novel memory systems are typically explored by hardware simulators that are slow and often have a simplified or obsolete abstraction of the CPU. This study presents PROFET, an analytical model that predicts how an application's performance and energy consumption changes when it is executed on different memory systems. The model is based on instrumentation of an application execution on actual hardware, so it already takes into account CPU microarchitectural details such as the data prefetcher and out-of-order engine. PROFET is evaluated on two real platforms: Sandy Bridge-EP E5-2670 and Knights Landing Xeon Phi platforms with various memory configurations. The evaluation results show that PROFET's predictions are accurate, typically with only 2% difference from the values measured on actual hardware. We release the PROFET source code and all input data required for memory system and application profiling. The released package can be seamlessly installed and used on high-end Intel platforms. CCS Concepts: • Computing methodologies → Model development and analysis; • Hardware → Dynamic memory.

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Section: Memory System Profilingcontrasting

confidence: 49%

Section: Memory System Profilingmentioning

confidence: 99%

Section: In-order Processorsmentioning

confidence: 99%

Section: Novelties Of the Presented Analytical Modelmentioning

confidence: 99%

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Profet

Radulovic

Verdejo

Carpenter

et al. 2019

Proc. ACM Meas. Anal. Comput. Syst.

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“…The first part is the time taken to execute the computation instructions. The second part is the time associated with fetching the data from storage to compute [21]. There is typically some degree of overlapping between these two components.…”

Section: Profiling Validity Performance Measurements Maymentioning

confidence: 99%

Using hardware counter-based performance model to diagnose scaling issues of HPC applications

Ding

Song

et al. 2018

Neural Comput & Applic

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Performance diagnosing for HPC applications can be extremely difficult due to their complicated performance behaviors. One hand, developers used to identify the potential performance bottlenecks by conducting detailed instrumentation, which may introduce significant performance overheads or even performance deviations. On the other hand, developers can only conduct small numbers of application runs for profiling the performance with the limitations on both computing resources and time duration. Meanwhile, the performance bottlenecks of HPC applications may vary with the degree of parallelism. To address these challenges, our paper proposes a systematic performance diagnosing method focusing on building an accurate and interpretable performance model with performance counters. Our method is able to diagnose the HPC application scaling issues by predicting its runtime and performance behaviors in different functions. After applying this modeling method on three real-world HPC applications, HOMME, CICE and OpenFoam, our evaluations show that our diagnosing method based on the performance model has the ability to diagnose the potential scaling issues, which is typically missed by the traditional performance diagnosing method and achieves about 10% prediction errors in a scale of 4096 MPI ranks on two problem sizes.Neural Computing and Applications (2019) 31:1563-1575 https://doi.org/10.1007/s00521-018-3496-z( 0123456789().,-volV) (0123456789(). ,-volV)

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Predictable Performance for QoS-Sensitive, Scalable, Multi-tenant Function-as-a-Service Deployments

Kuriata

Illikkal

2020

Lecture Notes in Business Information Processing

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In this paper we present the results of our studies focused on enabling predictable performance for functions executing in scalable, multi-tenant Function-as-a-Service environments. We start by analyzing QoS and performance requirements and use cases from the point of view of End-Users, Developers and Infrastructure Owners. Then we take a closer look at functions’ resource utilization patterns and investigate functions’ sensitivity to those resources. We specifically focus on the CPU microarchitecture resources as they have significant impact on functions’ overall performance. As part of our studies we have conducted experiments to research the effect of co-locating different functions on the compute nodes. We discuss the results and provide an overview of how we have further modified the scheduling logic of our containers orchestrator (Kubernetes), and how that impacted functions’ execution times and performance variation. We have specifically leveraged the low-level telemetry data, mostly exposed by the Intel® Resource Director Technology (Intel® RDT) [1]. Finally, we provide an overview of our future studies, which will be centered around node-level resource allocations, further improving a function’s performance, and conclude with key takeaways.

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Quantifying the Performance Impact of Memory Latency and Bandwidth for Big Data Workloads

Cited by 28 publications

References 20 publications

Profet

Profet

Using hardware counter-based performance model to diagnose scaling issues of HPC applications

Predictable Performance for QoS-Sensitive, Scalable, Multi-tenant Function-as-a-Service Deployments

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