Quantification and round influence on FPGA implemented algorithms for an OFDM radio interface

Vázquez, Jacinto Mata; Castan, B.; Campoy, Luis M.

doi:10.1109/pimrc.2004.1368777

Cited by 1 publication

(1 citation statement)

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“…QNE will introduce additional noise sources in the system which, in turn, will deteriorate the system performance. In this direction, only the report in [13] has analyzed the impact of the fixed point implementation in the synchronization system supported by simulations. However, a detailed analysis to balance synchronization performance (accuracy and precision) in terms of implemented bitwidth, is still unreported.…”

Section: Introductionmentioning

confidence: 99%

Impact of Quantization Noise Errors in FPGA Based WLAN Timing Synchronization with the Schmidl and Cox Algorithm

Gómez

Marrero

Koepp

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The implementation of accurate solutions to synchronize the transceiver's clocks in real-time operations plays a major role in the current development of communication systems. Considering the orthogonal frequency division multiplexing (OFDM)-based systems, adopted for the deployment of fifthgeneration mobile networks (5G), industrial networks, and the wireless local area network (WLAN) standard, several reported solutions focus on field-programmable gate array (FPGA) designs for the clock synchronization in real-time operations. However, reported solutions describe with minor details the impact of the introduced quantization noise error (QNE) based on the implemented bit-width. Their studies provide insights to implement digital solutions of reduced complexity. The current article provides theoretical expressions to characterize accuracy and precision while synchronizing the transmitter's clock. The presented analysis is intended to support designers to evaluate the clock synchronization design considering the bit-width for implementing the given system.

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Section: Introductionmentioning

confidence: 99%