Quality-Time Tradeoffs in Component-Specific Mapping

We show that continuously monitoring on-chip delays at the LUT-to-LUT link level during operation allows a field-programmable gate array to detect and self-adapt to aging and environmental timing effects. Using a lightweight (<4% added area) mechanism for monitoring transition timing, a Difference Detector with First-Fail Latch, we can estimate the timing margin on circuits and identify the individual links that have degraded and whose delay is determining the worst-case circuit delay. Combined with Choose-Your-own-Adventure precomputed, fine-grained repair alternatives, we introduce a strategy for rapid, in-system incremental repair of links with degraded timing. We show that these techniques allow us to respond to a single aging event in less than 190ms for the toronto20 benchmarks. The result is a step toward systems where adaptive reconfiguration on the time-scale of seconds is viable and beneficial.

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Quality-Time Tradeoffs in Component-Specific Mapping

Cited by 4 publications

References 32 publications

Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes

Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes

Self-Adaptive Timing Repair

Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)

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