QuADD: QUantifying Accelerator Disaggregated Datacenter Efficiency

Guleria, Anubhav; Lakshmi, J.; Padala, Chakri

doi:10.1109/cloud.2019.00064

Cited by 13 publications

(4 citation statements)

References 10 publications

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“…Following the trend for hardware specialization and the desire to better utilize resources as systems scale up, resource disaggregation across the system or a group of racks has been actively researched and deployed in commercial hyperscale datacenters in Google, Facebook, and others [17,55,64]. In addition, many studies focus on disaggregation of GPUs [35] and memory capacity [33,67].…”

Section: Resource Disaggregationmentioning

confidence: 99%

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A Case For Intra-rack Resource Disaggregation in HPC

Klenk

Cook

Teh

et al. 2022

ACM Trans. Archit. Code Optim.

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The expected halt of traditional technology scaling is motivating increased heterogeneity in high performance computing (HPC) systems with the emergence of numerous specialized accelerators. As heterogeneity increases, so does the risk of underutilizing expensive hardware resources if we preserve today’s rigid node configuration and reservation strategies. This has sparked interest in resource disaggregation to enable finer-grain allocation of hardware resources to applications. However, there is currently no data-driven study of what range of disaggregation is appropriate in HPC. To that end, we perform a detailed analysis of key metrics sampled in NERSC’s Cori, a production HPC system that executes a diverse open-science HPC workload. In addition, we profile a variety of deep learning applications to represent an emerging workload. We show that for a rack (cabinet) configuration and applications similar to Cori, a central processing unit (CPU) with intra-rack disaggregation has a 99.5% probability to find all resources it requires inside its rack. In addition, ideal intra-rack resource disaggregation in Cori could reduce memory and NIC resources by 5.36% to 69.01% and still satisfy the worst-case average rack utilization.

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Section: Resource Disaggregationmentioning

confidence: 99%

“…This capability is referred to as resource disaggregation. In datacenters, resource disaggregation has increased the utilization of GPUs and memory [19,33,35,50,64,67]. Such approaches usually employ a full-system solution where resources can be pooled from across the system.…”

Section: Introductionmentioning

confidence: 99%

A Case For Intra-rack Resource Disaggregation in HPC

Klenk

Cook

Teh

et al. 2022

ACM Trans. Archit. Code Optim.

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“…First, there is a growing need to support direct network connectivity with accelerators. This is essential, for example, in disaggregated data centers where network-accessible accelerators are pooled together [1,17,37], as well as in distributed computing applications such as DNN training [68,75]. Second, as network growth rate outpaces CPU capacity scaling, data-centers require inline acceleration of packet processing and network function virtualization applications to achieve high performance without wasting their tenants' CPU resources [32,65,94,98].…”

Section: Introductionmentioning

confidence: 99%

FlexDriver: a network driver for your accelerator

Eran¹,

Fudim

Malka

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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We propose a new system design for connecting hardware and FPGA accelerators to the network, allowing the accelerator to directly control commodity Network Interface Cards (NICs) without using the CPU. This enables us to solve the key challenge of leveraging existing NIC hardware offloads such as virtualization, tunneling, and RDMA for accelerator networking. Our approach supports a diverse set of use cases, from direct network access for disaggregated accelerators to inline-acceleration of the network stack, all without the complex networking logic in the accelerator.To demonstrate the feasibility of this approach, we build Flex-Driver (FLD), an on-accelerator hardware module that implements a NIC data-plane driver. Our main technical contribution is a mechanism that compresses the NIC control structures by two orders of magnitude, allowing FLD to achieve high networking scalability with low die area cost and no bandwidth interference with the accelerator logic.The prototype for NVIDIA Innova-2 FPGA SmartNICs showcases our design's utility for three different accelerators: a disaggregated LTE cipher, an IP-defragmentation inline accelerator, and an IoT cryptographic-token authentication offload. These accelerators reach 25 Gbps line rate and leverage the NIC for RDMA processing, VXLAN tunneling, and traffic shaping without CPU involvement. CCS CONCEPTS• Hardware → Hardware accelerators; Networking hardware; • Computer systems organization → Heterogeneous (hybrid) systems; Distributed architectures.

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“…INTRODUCTIONATA centers are being rapidly deployed in various organizations, including companies, institutions, and government offices. These centers host a growing number of applications like scientific computing, deep learning, and financial analysis, resulting in increased demand for bandwidth in data center communication networks [1][2][3]. Current data center networks are dominated by multi-tier electrical switch networks.…”

mentioning

confidence: 99%

Design and Analysis of a Nanosecond Burst-Mode CDR Using MATLAB/Simulink and Opti-System Co-Simulation

Zhang,

Li,

Yin

et al. 2023

IEEE Photonics J.

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Abstract-Optical packet switching (OPS) networks are promising to accommodate the growing traffic and reduce power consumption in data center communications. OPS networks with nanosecond switching time require nanosecond clock and data recovery (CDR) circuits. The nanosecond CDR can be achieved by utilizing a global frequency-synchronized reference clock for both transmitters (TX) and receivers (RX) and adopting a phase compensation scheme, which leads to predictably managed frequency and phase. However, the CDR still needs to be comprehensively evaluated considering various interferes. We add more analysis by developing a novel optoelectronic co-simulation system that combines the software Opti-system and MATLAB/Simulink. We set up a simple OPS network equipped with the CDR architecture using the simulation system. The feasibility of the CDR mechanism is validated, then various interferes are characterized to evaluate the CDR's stability, including the location variation of reference clock source, channel jitters, and carrier power variations. Index Terms-Data center networks, optical packet switching network, clock and data recovery, MATLAB/Simulink, Optisystem I. INTRODUCTIONATA centers are being rapidly deployed in various organizations, including companies, institutions, and government offices. These centers host a growing number of applications like scientific computing, deep learning, and financial analysis, resulting in increased demand for bandwidth in data center communication networks [1][2][3]. Current data center networks are dominated by multi-tier electrical switch networks. However, the bandwidth limitations of electrical processing chips and the power consumption associated with frequent electrical-optical conversions pose challenges [4][5][6]. To overcome these issues, optical packet switch (OPS) networks have emerged as a promising solution due to their high bandwidth capacity and elimination of electrical-optical conversions [7][8][9]. Given that many applications in data centers produce short traffic packets, OPS networks with nanosecond configuration time are required, which also necessitates the development of CDR with nanosecond locking time [10]. Existing burst-mode CDR Manuscript

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QuADD: QUantifying Accelerator Disaggregated Datacenter Efficiency

Cited by 13 publications

References 10 publications

A Case For Intra-rack Resource Disaggregation in HPC

A Case For Intra-rack Resource Disaggregation in HPC

FlexDriver: a network driver for your accelerator

Design and Analysis of a Nanosecond Burst-Mode CDR Using MATLAB/Simulink and Opti-System Co-Simulation

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