QOS Driven Network-on-Chip Design for Real Time Systems

Agarwal, Ankur; Mustafa, Mehmet; Pandya, Abhijit S.

doi:10.1109/ccece.2006.277852

Cited by 4 publications

(2 citation statements)

References 16 publications

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“…For example, for proper operation, all physical layout problems in a printed circuit board as well as VLSI designs involve constructing conductive (metallic) signal pathways that must be prevented from crossing each other; therefore, these problems naturally map into planar graphs. In VLSI chips, either the entire chip or large sections of the chip are modeled by planar graphs [35]. In [35], [36], the authors introduced turn prohibition in Network-On-Chips (NOCs) architectures, where multiple processing elements are networked on one VLSI chip in which the layout is planar.…”

Section: Turn Prohibitions For Planar Graphsmentioning

confidence: 99%

“…In VLSI chips, either the entire chip or large sections of the chip are modeled by planar graphs [35]. In [35], [36], the authors introduced turn prohibition in Network-On-Chips (NOCs) architectures, where multiple processing elements are networked on one VLSI chip in which the layout is planar. In this section, we present constructive upper bounds on the minimum fraction of turns, zðGÞ to be prohibited to break all cycles in any planar graph G.…”

Section: Turn Prohibitions For Planar Graphsmentioning

confidence: 99%

See 1 more Smart Citation

Minimal Sets of Turns for Breaking Cycles in Graphs Modeling Networks

Levitin

Karpovsky

Mustafa

2010

IEEE Trans. Parallel Distrib. Syst.

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The problem of preventing deadlocks and livelocks in computer communication networks, in particular, those with wormhole routing, is considered. The method to prevent deadlocks is to prohibit certain turns (i.e., the use of certain pairs of connected edges) in the routing process, in such a way that eliminates all cycles in the graph. We propose a new algorithm that constructs a minimal (irreducible) set of turns that breaks all cycles and preserves connectivity of the graph. The algorithm is tree-free and is considerably simpler than earlier cycle-breaking algorithms. We prove its properties and present lower and upper bounds for minimum cardinalities of cycle-breaking connectivity preserving sets for graphs of general topology as well as for planar graphs. In particular, the algorithm guarantees that not more than 1=3 of all turns in the network become prohibited. We also present experimental results on the fraction of prohibited turns, the distance dilation, as well as on the message delivery times and saturation loads for the proposed algorithm in comparison with known tree-based algorithms. The proposed algorithm outperforms substantially the tree-based algorithms in all characteristics considered.

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Section: Turn Prohibitions For Planar Graphsmentioning

confidence: 99%

Section: Turn Prohibitions For Planar Graphsmentioning

confidence: 99%

Minimal Sets of Turns for Breaking Cycles in Graphs Modeling Networks

Levitin

Karpovsky

Mustafa

2010

IEEE Trans. Parallel Distrib. Syst.

Self Cite

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Quality of service routing algorithm in the torusbased network on chip

Wang

2009

2009 IEEE 8th International Conference on ASIC

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Network on chip (NoC) is an emerging area and recognized as the future methodology for chip design. Provision ofQoS in network on chip is a challenging problem and receives much attention recently. A QoS routing scheme is proposed to support various traffic with different QoS requirements in the interconnection networks of NoC. Specifically, three distributed QoS routing algorithms are developed based on different blocking handling methods. The algorithms use local information and are proven to be deadlock free and livelock free. Various strategies to handle blocking are utilized to lower the call failure rate. Simulations are carried on 3D torus topology. The results show that the proposed algorithms increase the network capacity by 30-40% (compared with the dimension order algorithm) and by 20-30% (compared with Duato's algorithm). 1

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A Deep Learning Network-on-Chip (NoC)-Based Switch-Router to Enhance Information Security in Resource-Constrained Devices

Shahrani¹,

Rizwan²,

Algarni³

et al. 2023

J CIRCUIT SYST COMP

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In a resource-constrained environment of the 21st century, the use of hardware-based reconfigurable systems such as Field Programmable Gate Array (FPGAs) is considered an effective way to enhance information security. In comparison with traditional custom circuitry that does not give a flexible approach, it is observed that the reconfigurable hardware shows an excellent potential for cyber security by increasing hardware speeds and flexibility. Therefore, in a quest to integrate multi-core systems, the Network-on-Chip (NoC) has become one of the popular widespread techniques to maximize router security. Due to the significant overhead of chip space and the power consumption of the routers, it is substantially more expensive to construct as compared to a bus-based system. The control component (CC) interacts with the networks that inject packets based on router switching and activity. These control components are coupled with each network to produce a system of controlled networks. The system is further linked with CFM or a Centralized Fabric Manager, which serves as the network’s focal point. After that, the CFM runs the algorithm regularly. The analytic parameters comprise flip flop, power, latency, number of lookup tables (LUTs), and throughput. In the proposed method, the number of LUTs is [Formula: see text], the flip flop is [Formula: see text], the power is [Formula: see text]W, the latency is 5941[Formula: see text]ns, and the planned throughput is 0.56 flits/cycle. Results indicate that the crossbar switch reduces errors and minimizes the delay in the architecture’s outcome level, which further overcomes the descriptions of performance, power throughput, and area delay parameters. The findings of the research can be useful to enhance information security among lightweight devices besides minimizing the chances of network attacks in today’s dynamic and complex cyberspace.

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QOS Driven Network-on-Chip Design for Real Time Systems

Cited by 4 publications

References 16 publications

Minimal Sets of Turns for Breaking Cycles in Graphs Modeling Networks

Minimal Sets of Turns for Breaking Cycles in Graphs Modeling Networks

Quality of service routing algorithm in the torusbased network on chip

A Deep Learning Network-on-Chip (NoC)-Based Switch-Router to Enhance Information Security in Resource-Constrained Devices

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