QCA based cost efficient coplanar 1 × 4 <scp>RAM</scp> design with set/reset ability

Naz, Syed Farah; Ahmed, Suhaib; Ko, Seok‐Bum; Shah, Ambika Prasad; Sharma, Sparsh

doi:10.1002/jnm.2946

Cited by 7 publications

(6 citation statements)

References 33 publications

(43 reference statements)

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“…As illustrated in Figure 1A, electrons can tunnel between the dots and achieve cell polarization of P = 1 (logic 1) or P = 0 (logic 0) 7,8 . Inverter and majority gates are two key gates for logical computations in quantum‐dot CA technology, as depicted in Figure 1B,C 9–12 . The majority gate casts votes among the input cells and sends the inputs' majority polarization to the output cell.…”

Section: The History Of the Quantum‐dot Camentioning

confidence: 99%

“…7,8 Inverter and majority gates are two key gates for logical computations in quantum-dot CA technology, as depicted in Figure 1B,C. [9][10][11][12] The majority gate casts votes among the input cells and sends the inputs' majority polarization to the output cell. The majority gate becomes a logic "AND" or "OR" gate by setting one of the inputs to binary "0" or "1.…”

Section: The History Of the Quantum-dot Camentioning

confidence: 99%

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Design and optimization of a fault‐tolerant demultiplexer based on nano‐scale quantum‐dots

Zhou

2023

Int J Numerical Modelling

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In quantum electronics, quantum-dot cellular automata (CA) is a technology to replace current transistor-based technologies. It provides low-power, incredibly dense, and high-speed constructions at a nano-scale. Quantum-dot CA is a revolutionary nano-scale technology that overcomes various restrictions in metal-oxide technology and simplifies the construction of digital integrated circuits. On the other hand, the demultiplexer is a valuable component for optimizing the entire process in logical design. So, proper cell placement and associated clock zone become the most important design requirement for effective logic operation in demultiplexer. Also, redundancy in fault-tolerant circuits can increase the dependability of digital circuits. However, in this area, the studies are not adequate, and most of them suffer from improper use of clocking systems and inefficient circuit features such as fault-tolerant. As a result, the current study demonstrates a unique quantum-dot CA-based faulttolerant 1:2 demultiplexer design. The proposed method is verified by implementing the fault-tolerant gates and cell redundancy. Also, we look at the layouts' cells, area, latency, single-cell missing, single-cell displacement, and additional single-cell. We also use the famous simulator, QCADesigner, to model the proposed design. The proposed fault-tolerant 1:2 demultiplexer's effectiveness is also discussed. Sixty-eight cells and 0.04 μm 2 of occupied space make up the unique fault-tolerant 1:2 demultiplexer. The results showed that the proposed design is completely faults-tolerance regarding tolerant missing, displaced, and additional single cells faults.

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Section: The History Of the Quantum‐dot Camentioning

confidence: 99%

Section: The History Of the Quantum-dot Camentioning

confidence: 99%

Design and optimization of a fault‐tolerant demultiplexer based on nano‐scale quantum‐dots

Zhou

2023

Int J Numerical Modelling

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“…The third yield is considered a garbage value. M-based logic expressions for D 0 and D 1 of the 1-to-2 decoder circuit are presented in ( 4) and (5).…”

Section: Qca1 Gatementioning

confidence: 99%

“…International Technology Roadmap for Semiconductors (ITRS) 4 accounts for a few potential options. Quantum‐dot cellular automata (QCA) is one of these choices 5–8 …”

Section: Introductionmentioning

confidence: 99%

Nano‐scale design of full adder and full subtractor using reversible logic based decoder circuit in quantum‐dot cellular automata

Das

2023

Int J Numerical Modelling

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This paper presents a reversible nano‐scale decoder circuit. The decoder is designed by utilizing the new quantum‐dot cellular automata (QCA) format of the QCA1 gate. This QCA1 gate provides 34.25% less cell count with 54.37% less area than the best existing designs. Thus, the proposed QCA1 gate provides less area considering the best existing state‐of‐the‐art plans. The IBMQ‐based quantum realization of the QCA1 gate is also illustrated. The reversible full adder and subtractor circuits by employing the proposed decoder are likewise explored in this paper. A four‐input reversible OR‐gate is structured and concatenates with a decoder circuit to frame the circuit for full adder and subtractor. The energy dissipation by these QCA circuits is assessed to build up that QCA is an attractive option to CMOS for realizing reversible logic designs. The implemented results are compared with the truth table to ensure operational accuracy. The planned circuits can be utilized to structure reversible designs for nano‐communication.

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“…Furthermore, using QCA technology can decrease the number of gate counts and minimize the occupied area within the CLA circuit. In other words, this unique technology with a simple quantum cell and a simple formulation can fix all the previous shortcomings in the CLA circuit [20]. Therefore, this paper suggests implementing effective four and sixteen CLA utilizing a full adder using QCA technology.…”

Section: Introductionmentioning

confidence: 99%

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

Ahmadpour,

Jafari Navimipour

2023

Phys. Scr.

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There is a requirement and a desire to develop reliable and energy-efficient circuit designs that adapt to the expanding field of low-power circuit engineering in the VLSI domain based on nanotechnology. The quantum-dot cellular automata (QCA) technology possesses the potential to supplant the conventional, complementary metal-oxide-semiconductor (CMOS) technology in low-power nano-scale applications due to its diminutive cell dimensions, dependable circuitry architecture, and robust structural integrity. On the other hand, the carry look-ahead adder (CLA) is one of the vital circuits in digital processing utilized in diverse digital applications. In addition, for the design of this essential circuit, the occupied area and the delay play the primary role because using a simple formulation can reduce the occupied area, energy consumption, and the number of gates count. In the previous structures, high delay and use of traditional technology (like CMOS) caused an increase in the number of gate counts and occupied areas. Using QCA technology, simple quantum cells, and a low delay, all the previous shortcomings can be resolved to reduce the number of gate counts and low occupied area in the CLA circuit. This paper proposes a new method that helps the propagation characteristics generate suitable signals to reduce the number of gate counts based on adders in QCA technology. Several new blocks are used to design fast binary adders. Finally, an optimal four and 16-bit CLA circuit will be proposed based on the adder circuit. Furthermore, the execution and experimentation of outcomes are carried out utilizing QCADesigner-2.0.3. The simulation-based comparison of values justified the proposed design’s accuracy and efficiency. The simulation results demonstrate that the proposed circuit has a low area and quantum cell.

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QCA based cost efficient coplanar 1 × 4 RAM design with set/reset ability

Cited by 7 publications

References 33 publications

Design and optimization of a fault‐tolerant demultiplexer based on nano‐scale quantum‐dots

Design and optimization of a fault‐tolerant demultiplexer based on nano‐scale quantum‐dots

Nano‐scale design of full adder and full subtractor using reversible logic based decoder circuit in quantum‐dot cellular automata

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

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