2014
DOI: 10.1145/2654822.2541961
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Q100

Abstract: In this paper, we propose Database Processing Units, or DPUs, a class of domain-specific database processors that can efficiently handle database applications. As a proof of concept, we present the instruction set architecture, microarchitecture, and hardware implementation of one DPU, called Q100. The Q100 has a collection of heterogeneous ASIC tiles that process relational tables and columns quickly and energy-efficiently. The architecture uses coarse grained in- structions that manipulate streams of data, t… Show more

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Cited by 19 publications
(4 citation statements)
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“…Many recent works [26], [30], [32], [34]- [36], [40], [47], [49], [57], [59], [63]- [66] have tried to accelerate relational database queries with ASIC, FPGA, and GPU. Q100 [64] and Andrea et al [49] are typical database accelerator composed of ASIC tiles for each database primitive. Many prior works [30], [32], [35], [59], [63] have accelerated several relational operations using various hardware architectures on FPGA.…”
Section: Related Workmentioning
confidence: 99%
“…Many recent works [26], [30], [32], [34]- [36], [40], [47], [49], [57], [59], [63]- [66] have tried to accelerate relational database queries with ASIC, FPGA, and GPU. Q100 [64] and Andrea et al [49] are typical database accelerator composed of ASIC tiles for each database primitive. Many prior works [30], [32], [35], [59], [63] have accelerated several relational operations using various hardware architectures on FPGA.…”
Section: Related Workmentioning
confidence: 99%
“…Accelerating Data Analytics On-chip accelerator Q100 [47] exploits pipeline in query processing with heterogeneous processing cores to minimize the memory access. Mondrian and Polynesia [7], [12] integrate circuits in logic die of 3D stacked memory, which is much further from the DRAM cells and loses the internal bandwidth.…”
Section: Related Workmentioning
confidence: 99%
“…There have been two main efforts to implement query processing on hardware, namely ASIC-based and FPGA-based solutions [141,62]. The work in [141] presents an ASIC-based method with heterogeneous compute tiles which manipulate rows and handle query processing operations in a coarse grain way.…”
Section: Query Processing Hardware Designmentioning
confidence: 99%
“…There have been two main efforts to implement query processing on hardware, namely ASIC-based and FPGA-based solutions [141,62]. The work in [141] presents an ASIC-based method with heterogeneous compute tiles which manipulate rows and handle query processing operations in a coarse grain way. In order to manipulate streams of data according to the given query, the authors present spatial and temporal planning which enables/disables compute units along a predefined data path.…”
Section: Query Processing Hardware Designmentioning
confidence: 99%