Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design

Makrani, Hosein Mohammadi; Farahmand, Farnoud; Sayadi, Hossein; Bondi, Sara; Dinakarrao, Sai Manoj Pudukotai; Homayoun, Houman; Rafatirad, Setareh

doi:10.1109/fpl.2019.00069

Cited by 32 publications

(12 citation statements)

References 31 publications

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“…The overall workflow of timing and resource usage prediction is concluded in Figure 2. This workflow is first proposed by Dai et al [30] and augmented by Makrani et al [105] and Ferianc et al [37]. The main methodology is to train an ML model that takes HLS reports as input and outputs a more accurate implementation report without conducting the time-consuming post-implementation.…”

Section: Machine Learning For Results Estimationmentioning

confidence: 99%

“…ML techniques have been applied to improve HLS tools from the following three aspects: fast and accurate result estimation [30,37,105,106,140,161,169], refining conventional DSE algorithms [74,104,146], and reforming DSE as an active-learning problem [92,93,109,177]. In addition to achieving good results on individual problems, previous studies have also introduced new generalizable techniques about feature engineering [30,105,106,161,169], selection and customization of ML models [140], and design space sampling and searching strategies [93,109,177].…”

Section: High Level Synthesismentioning

confidence: 99%

“…Makrani et al [105] model timing as a regression problem, and use the Minerva tool [36] to obtain results in terms of maximum clock frequency, throughput, and throughput-to-area ratio for the RTL code generated by the HLS tool. Then, an ensemble model is proposed to conduct estimation, which combines linear regression, neural network, SVM and random forest, and achieve an accuracy higher than 95%.…”

Section: Inaccuratementioning

confidence: 99%

“…The output is the speedup estimation on the target FPGA over an ARM A-9 processor. This method is similar to Dai et al [30] and Makrani et al [105] in that they all take the features in HLS reports as input and aim to avoid the time-consuming post-implementation. The main difference is that the input and output features in XPPE are from different platforms.…”

Section: Hls Toolmentioning

confidence: 99%

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Machine Learning for Electronic Design Automation: A Survey

Huang

et al. 2021

Preprint

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With the down-scaling of CMOS technology, the design complexity of very large-scale integrated (VLSI) is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 90s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interests in incorporating ML to solve EDA tasks. In this paper, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

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Section: Machine Learning For Results Estimationmentioning

confidence: 99%

Section: High Level Synthesismentioning

confidence: 99%

Section: Inaccuratementioning

confidence: 99%

Section: Hls Toolmentioning

confidence: 99%

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Machine Learning for Electronic Design Automation: A Survey

Huang

et al. 2021

Preprint

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“…More traditional models have also been used. For example, Pyramid [22] used an ensemble of traditional ML models including Random Forest, Support Vector Machine (SVM), and Linear Regression to predict the resource usage of an HLS design on an FPGA. Among these models, the Graph Neural Networks (GNN) models (GraphSage and GCN) stand out from other models because of their accuracy and elegance when performing circuit analysis.…”

Section: Background and Motivationmentioning

confidence: 99%

SNS's not a synthesizer

Kjellqvist

Wills

2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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The number of transistors that can fit on one monolithic chip has reached billions to tens of billions in this decade thanks to Moore's Law. With the advancement of every technology generation, the transistor counts per chip grow at a pace that brings about exponential increase in design time, including the synthesis process used to perform design space explorations. Such a long delay in obtaining synthesis results hinders an efficient chip development process, significantly impacting time-to-market. In addition, these large-scale integrated circuits tend to have larger and higher-dimension design spaces to explore, making it prohibitively expensive to obtain physical characteristics of all possible designs using traditional synthesis tools.In this work, we propose a deep-learning-based synthesis predictor called SNS (SNS's not a Synthesizer), that predicts the area, power, and timing physical characteristics of a broad range of designs at two to three orders of magnitude faster than the Synopsys Design Compiler while providing on average a 0.4998 RRSE (root relative square error). We further evaluate SNS via two representative case studies, a general-purpose out-of-order CPU case study using RISC-V Boom open-source design and an accelerator case study using an in-house Chisel implementation of DianNao, to demonstrate the capabilities and validity of SNS. CCS CONCEPTS• Hardware → Integrated circuits; High-level and registertransfer level synthesis; • Computing methodologies → Neural networks.

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