PVT compensation in Mie Fujitsu 55 nm DDC: A standard-cell library based comparison

Müller, Thomas Christoph; Nagel, Jean-Luc; Pons, Marc; Severac, Daniel; Hashiba, Katsuhiro; Sawada, Shin–ichi; Miyatake, Katsuji; Emery, Stephane; Burg, Andreas

doi:10.1109/s3s.2017.8309246

Cited by 3 publications

(3 citation statements)

References 4 publications

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“…Adapting the BB to the operating point enables to reduce the adverse effect of sub-threshold operation on timing across process and temperature variations (e.g. worst case corner distance from 21x to 0.2x [93]). This allows to implement a wide range of timing-clean operating points from fast to slow and low power.…”

Section: 22mentioning

confidence: 99%

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Jokic¹,

Azarkhish²,

Bonetti³

et al. 2022

ACM Trans. Embed. Comput. Syst.

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Implementing embedded neural network processing at the edge requires efficient hardware acceleration that combines high computational throughput with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly being adapted to support the improved functionalities. Hardware designers can refer to a myriad of accelerator implementations in the literature to evaluate and compare hardware design choices. However, the sheer number of publications and their diverse optimization directions hinder an effective assessment. Existing surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effects of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. In contrast to previous surveys, this work provides a quantitative overview of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. The list of optimizations and their quantitative effects are presented as a construction kit, allowing to assess the design choices for each building block individually. Reported optimizations range from up to 10’000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators.

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Section: 22mentioning

confidence: 99%

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Jokic¹,

Azarkhish²,

Bonetti³

et al. 2022

ACM Trans. Embed. Comput. Syst.

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“…However, it is more common to consider unique derating factors for each OC t , for each cell within each OC t , or for each timing arc within each cell. In this paper we refer to derating factors as being unique for each of T P D and T tran , cell c, and timing arc a as in [34]. For T P D under given OC b , c, a, T tran , and C l condition, the derating factor for OC t is applied as follows:…”

Section: Cross-corner Variation Modelsmentioning

confidence: 99%

Cross-Corner Delay Variation Model for Standard Cell Libraries

Kim

Joo²,

Park

et al. 2021

IEEE Access

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For timing closure of logic circuits, circuit designers must perform sign-offs on a variety of process, voltage, and temperature (PVT) conditions. Designs of advanced logic circuits involve a multitude of voltage islands and operating modes, each of which requires delay characterizations at nearby PVT corners. Furthermore, advanced technologies nodes suffer from corner explosion: while the impact of PVT variations is being exacerbated, process variations are also diversifying, increasing the number of operating conditions exponentially. This paper revisits the importance of cross-corner timing estimations and proposes a delay variation model to mitigate such corner explosion. Our objective is to reduce PVT corner characterization effort for timely static timing analysis on an exploding number of operating conditions. Our proposed Decomposed Propagation Vector Variation Model (DPVVM) decomposes propagation delay and timing constraints into the driving by the receiver cell and its driver cell; by scaling them separately, delay characterization effort is reduced to a fraction of time while realizing accurate timing estimations. We also propose Multi-Dimension Recomposition (MDR) scheme, which exploits a multitude of pre-characterized corners to further improve the consistency of cross-corner timing estimations. As a result, with only 8.0% of a corner characterization effort compared to the full-characterization, DPVVM combined with MDR achieves overall cross-corner timing estimation errors of 4.8% and 5.6% for single cells and complex logic circuits-or improvements of 69% and 61% over the conventional derating method, respectively. Our proposed method's characterization overhead is 11% over the conventional derating method; the overhead is marginal, accounting for only 0.76% of a full-characterization time.

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“…The logical effort approaches [3][4] were introduced for sub-VT transistor sizing and critical path optimization. In addition, several effects were leveraged to improve the performance of cells in ULV circuits, including inverse narrow width effect (INWE) [5][6][7], reverse short channel effect (RSCE) [8][9][10], and body biasing [11][12]. Jun et al [13] reported a near-VT cell library which utilized INWE, RSCE, and forward body biasing (FBB) techniques, and demonstrated better power-delay-product (PDP) as well as energy-delay-product (EDP) in circuits design over conventional libraries.…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits

Zhang

Sun

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Commercial multi-threshold standard logic cell libraries are designed for nominal super-threshold circuits. If blindly used at near-and sub-threshold voltages, such libraries exhibit excessively coarse granularity in driving strength, leading to sub-optimal logic synthesis and placement-androuting results. To tackle this problem, a holistic methodology for designing a near-and sub-threshold standard cell library that has fine driving strength granularity is presented in this paper. Meanwhile, the proposed methodology leverages inverse narrow width effect, reverse short channel effect and forward body biasing to modulate the driving strength at low area overheads. Based on the proposed methodology, we develop a 65nm multi-threshold-voltage, multi-channel-length library and benchmark it against the commercial library across several common circuits. The results show a 26.6% reduction in power-delay product, a 28.1% reduction in energy-delay product, and a 27.0% reduction in leakage power at 5.8% area overhead on average, confirming the efficiency of the methodology in near-and sub-threshold digital circuits design.

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PVT compensation in Mie Fujitsu 55 nm DDC: A standard-cell library based comparison

Cited by 3 publications

References 4 publications

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Cross-Corner Delay Variation Model for Standard Cell Libraries

An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits

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