PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping

Du, Yiran; Li, Wei; Dai, Zibin; Liu, Nan

doi:10.1109/tvlsi.2020.2972392

Cited by 23 publications

(15 citation statements)

References 20 publications

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“…Table 9 shows the overall comparison between the proposed reconfigurable cryptographic accelerator and the state-of-the-art designs based on ASIC implementation. The benchmark table uses AES-128 algorithm for a fair comparison, which has been widely adopted in many studies [ 10 , 11 , 12 ].…”

Section: Implementation Results and Discussionmentioning

confidence: 99%

“…As shown in Table 9 , the proposed reconfigurable cryptographic accelerator achieves the minimum area, the lowest power consumption, and the highest energy efficiency and area efficiency—mainly due to the different implementation methods of various cryptographic algorithms (DES/AES/SM4 and SHA-1/SHA-256/SM3). The implementation method in [ 10 , 11 , 12 ] is designing a unified reconfigurable engine based on the coarse-grained reconfigurable array (CGRA), which can realize a more flexible reconfigurable architecture supporting various cryptographic algorithms including block ciphers, stream ciphers and hash functions, etc. Specifically, in the three designs, memories are used to store configuration information, FIFOs are used to buffer intermediate data, and reconfigurable processing element arrays including a large number of reconfigurable cells, multiplexers and routers are used to realize a flexible reconfigurable architecture.…”

Section: Implementation Results and Discussionmentioning

confidence: 99%

“…Du et al [ 11 ] have reported a coarse-grained reconfigurable cryptographic logic array and an intelligent mapping algorithm for different cryptographic algorithms, such as DES/AES/SM4/SHA-256, etc. Deng et al [ 12 ] have reported a coarse-grained reconfigurable cryptographic processor, which can implement all the commonly used cryptographic algorithms, including DES, AES, SM4, SHA-256, SM3, etc.…”

Section: Introductionmentioning

confidence: 99%

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Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices

Zhang

Liu

Zhao

et al. 2022

Sensors

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Achieving low-cost and high-performance network security communication is necessary for Internet of Things (IoT) devices, including intelligent sensors and mobile robots. Designing hardware accelerators to accelerate multiple computationally intensive cryptographic primitives in various network security protocols is challenging. Different from existing unified reconfigurable cryptographic accelerators with relatively low efficiency and high latency, this paper presents design and analysis of a reconfigurable cryptographic accelerator consisting of a reconfigurable cipher unit and a reconfigurable hash unit to support widely used cryptographic algorithms for IoT Devices, which require block ciphers and hash functions simultaneously. Based on a detailed and comprehensive algorithmic analysis of both the block ciphers and hash functions in terms of basic algorithm structures and common cryptographic operators, the proposed reconfigurable cryptographic accelerator is designed by reusing key register files and operators to build unified data paths. Both the reconfigurable cipher unit and the reconfigurable hash unit contain a unified data path to implement Data Encryption Standard (DES)/Advanced Encryption Standard (AES)/ShangMi 4 (SM4) and Secure Hash Algorithm-1 (SHA-1)/SHA-256/SM3 algorithms, respectively. A reconfigurable S-Box for AES and SM4 is designed based on the composite field Galois field (GF) GF(((22)2)2), which significantly reduces hardware overhead and power consumption compared with the conventional implementation by look-up tables. The experimental results based on 65-nm application-specific integrated circuit (ASIC) implementation show that the achieved energy efficiency and area efficiency of the proposed design is 441 Gbps/W and 37.55 Gbps/mm2, respectively, which is suitable for IoT devices with limited battery and form factor. The result of delay analysis also shows that the number of delay cycles of our design can be reduced by 83% compared with the state-of-the-art design, which shows that the proposed design is more suitable for applications including 5G/Wi-Fi/ZigBee/Ethernet network standards to accelerate block ciphers and hash functions simultaneously.

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Section: Implementation Results and Discussionmentioning

confidence: 99%

Section: Implementation Results and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices

Zhang

Liu

Zhao

et al. 2022

Sensors

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show abstract

“…Systolic CGRA architectures generally perform somewhat better but are less flexible than Blocks. Examples of such architectures are PHVArray [42] (20 pJ/op, 550 nm), REMUS_HPP [44] (5.5 pJ/op, 65 nm), and REMUS_LPP [44] (1.3 pJ/op, 65 nm). The latter two are video decoding optimized systolic arrays with many function units (256), which helps to amortize overhead.…”

Section: Summary Of Resultsmentioning

confidence: 99%

Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture

Wijtvliet

Kumar

Corporaal

2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Demand for coarse grain reconfigurable architectures (CGRAs) has significantly increased in recent years as architectures need to be both energy efficient and flexible. However, most CGRAs are optimized for performance instead of energy efficiency. In this work, a novel paradigm for reconfigurable architectures, Blocks, is presented. Blocks uses two separate circuit-switched networks, one for control and one for the data path. This enables the runtime construction of energy-efficient application-specific VLIW-SIMD processors on a reconfigurable fabric. Its energy efficiency is demonstrated by comparing Blocks to four reference architectures, a VLIW, an SIMD, a commercial low-power microprocessor, and a traditional CGRA. All comparisons are based on commercial low-power 40-nm CMOS layout, including memories. Results show that Blocks can achieve a mean total energy reduction of 2.05×, 1.84×, 8.01×, and 1.22× over a VLIW, an SIMD, an energyefficient microprocessor and a traditional CGRA, respectively. At the same time, Blocks delivers equal or higher performance per area due to its ability to adapt to applications by reconfiguration.

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“…CGCLA adds data paths and interconnection resources between PEs, and enables the dynamic configuration rate to be increased. And in a recent study 8 , Du Y et al presented a CGRA cryptographic logic array named PVHArray, and implemented it on a 55 nm process COMS chip. PVHArray uses a hierarchical interconnection network instead of a single network in its computing array, and combines with ant colony algorithms to optimize the mapping of encryption algorithms, reducing the compilation time of the encryption algorithm by 38%.…”

Section: Introductionmentioning

confidence: 99%

A reconfigurable design of satellite in-orbit encryption algorithms based on FPGA

Cheng

Yang

et al. 2022

5th International Conference on Computer Information Science and Application Technology (CISAT 2022)

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PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping

Cited by 23 publications

References 20 publications

Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices

Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices

Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture

A reconfigurable design of satellite in-orbit encryption algorithms based on FPGA

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