pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing

Abstract

This paper presents an ameliorated design of pvFPGA, which is a novel system design solution for virtualising an FPGA-based hardware accelerator by a virtual machine monitor (VMM). The accelerator design on the FPGA can be used for accelerating various applications, regardless of the application computation latencies. In the implementation, we adopt the Xen VMM to build a paravirtualised environment, and a Xilinx Virtex-6 as an FPGA accelerator. The data transferred between the x86 server and the FPGA accelerator through direct memory access (DMA), and a streaming pipeline technique is adopted to improve the efficiency of data transfer. Several solutions to solve streaming pipeline hazards are discussed in this paper. In addition, we propose a technique, hyper-requesting, which enables portions of two requests bidding to different accelerator applications to be processed on the FPGA accelerator simultaneously through DMA context switches, to achieve request level parallelism. The experimental results show that hyper-requesting reduces request turnaround time by up to 80%.Keywords: field-programmable gate array; FPGA; hardware accelerator; virtualisation; hyperrequesting; streaming pipeline; DMA context switch.Reference to this paper should be made as follows: Wang, W., Bolic, M. and Parri, J. (2017) 'pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing', Int.

WITHDRAWN: RPUGuard: a Building Block for Next-Generation MPSoCs Hypervisors toward Mixed-Criticality Systems

“…There are several surveys that attempt to describe the current state of the art in FPGA virtualization [51] [52] [53]. It is possible to distinguish two directions to FPGA virtualization in the literature: the FPGA used as a shared hardware accelerator resource between VMs [54] [55], and the FPGA used to improve the features of the hypervisor [56] [57]. Following the latter approach, several papers focus on increasing the predictability of the hypervisor leveraging FPGA for real-time purposes.…”