Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture

FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST

“…It is a difficult task to make a balanced relationship among the fault coverage, TAT and power consumption because improving the Design for Testability (DFT) to meet one constraint usually would aggravate the others [2]. For shorting the TAT of POST, many means focused on improving the test architecture involving the scan structure design or test scheduling, such as the scan chain partitioning [3], scan-shift clock reusing [4], TMS (Tri-Modal Scan) test [5] and capture-per-cycle hybrid-TPI [6]. However, these means still suffer from the problems in terms of the large hardware overhead, complex ATPG applications, and huge elapsed times for the simulation (logic & fault).…”

Design for test methods to reduce test set size

“…The test cube merging integrated with the staggered ATPG can be summarized as follows: We deploy an approach similar to that of [59], by inserting observation points directly at the inputs of certain regular scan cells to capture test results that otherwise would be lost, due to the scan shift mode separating the scan cells from a combinational part of a design (see Figure 4 With the same idea of selecting suitable scan cells that can cover more test cubes, as well as detect additional faults during staggered pattern simulation, instead of learning the information from a complete ATPG run, we can perform a structural tracing based on the fault list to obtain a fault propagation profile for the scan cells. The propagation analysis is shown in Figure 4.7 and can be described as follows:…”

“…In this section, we will discuss the difference between test- [49], [50], [51], [52], [53], [54], [55], [56], [57], [58], [59], [60], [61], [62], leverage the advantage of test-per-clock to apply test patterns in shorter time. These earlier methods include build-in logic block observers (BILBO) [54], a circular self-test path [51], [53], [55], [57], E-BIST [50], [56], and some techniques applying deterministic test patterns [52], [61], [62].…”

“…59]. Unlike the dynamic scan structure used by TMS[58], this method employs dedicated shadow registers (observation points) with XOR gates to capture test results during the scan shift to fortuitously detect cell-aware faults with test patterns generated for stuck-at faults.…”

“…Results in[59] show that, with all scan cells shadowed, this method can achieve 30% -90% test pattern reduction for designs with highly observable sites (scan cells that can easily capture many fault effects), and for more complicated industrial designs with limited observation of faults, this method achieves 5% -10% test pattern reduction for stuck-at faults after all the scan cells are shadowed. In Chapter 4, we will present an approach that uses a similar idea as[59] to insert observation test points to capture fault effects during shift cycles. Different from [59], we develop a dedicated test generation procedure to produce effective test-perclock patterns based on this test scheme.…”