Proceedings of the 2020 ACM SIGMOD International Conference on Management of Data 2020
DOI: 10.1145/3318464.3389705
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Cited by 50 publications
(5 citation statements)
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“…Different communication interfaces might play a key role in alleviating this effect, such as streaming [14], where queries can be fed to the accelerator, executed, and returned while the rest of the stream is still being processed. Future developments of interconnects, such as CXL and NVLink, and accelerator interfaces have the potential of lifting the current limitations and enable new use cases [15,17]. Notably, GPU starvation by lack of incoming data from one of the for NVIDIA's CPU architecture, which provides a much higher bandwidth between CPU and GPU than conventional approaches [7,8].…”
Section: Optimising the Input Channelmentioning
confidence: 99%
See 1 more Smart Citation
“…Different communication interfaces might play a key role in alleviating this effect, such as streaming [14], where queries can be fed to the accelerator, executed, and returned while the rest of the stream is still being processed. Future developments of interconnects, such as CXL and NVLink, and accelerator interfaces have the potential of lifting the current limitations and enable new use cases [15,17]. Notably, GPU starvation by lack of incoming data from one of the for NVIDIA's CPU architecture, which provides a much higher bandwidth between CPU and GPU than conventional approaches [7,8].…”
Section: Optimising the Input Channelmentioning
confidence: 99%
“…They also show the increasing amount of compute power, network, and memory bandwidth needed on the CPU side to be able to match the throughput of the accelerator. A number of other studies have also explored this problem [11,17,32] confirming that the advantages a hardware accelerator can bring are bound by the ability to generate enough load on it, often leading to a situation where the accelerated system is larger than the initial one. This issue is one of the reasons why new processor architectures are emerging that try to avoid these bottlenecks [7,8] and new standards for peripheral interconnects are appearing [6,24,30].…”
Section: Introductionmentioning
confidence: 99%
“…Генерация кода для оператора (цепочки операторов, оканчивающихся pipeline-breaker -оператором, требующим готовности всего результата до исполнения следующего), совместно с пакетной обработкой данных позволяет значительно сократить пересылку данных по медленной PCIe и, тем самым, добиться кратного роста скорости исполнения запроса [2]. Увеличение пропускной способности шины демонстрирует значительное повышение производительности исполнения запроса в целом [3], даже в случае входных данных, не помещающихся в память целиком (morsel-driven).…”
Section: Hybrid Execution Of Queries To Analytical Databasesunclassified
“…In the age of ever‐increasing data volumes, the overhead of data transfers is a major inhibitor of further performance improvements on many levels. In heterogeneous compute architectures, the overhead of transferring data (e.g., between host and graphics processing unit (GPU) memory) can still have a major impact on the overall performance, even when the latest state‐of‐the‐art interconnection technologies are used such as NVLink‐2 on the intra‐node level 1,2 and InfiniBand EDR on the inter‐node level 1 . For many data‐intensive applications, scaling out to multiple nodes is the most feasible strategy to satisfy their resource demands.…”
Section: Introductionmentioning
confidence: 99%