PuDianNao

Liu, Daofu; Liu, Shaoli; Zhou, Junlin; Zhou, Shuai; Teman, Olivier; Feng, Xiaobing; Zhou, Xuehai; Chen, Tianshi

doi:10.1145/2694344.2694358

Cited by 168 publications

(9 citation statements)

References 32 publications

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“…Storage Constraints: Tens of TBs of storage space is needed to store the prior maps in large environments required by autonomous driving systems to localize the vehicle (e.g., 41 TB for an entire map of the U.S.).…”

Section: Storage Constraintsmentioning

confidence: 99%

The Architectural Implications of Autonomous Driving

et al. 2018

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Autonomous driving systems have attracted a signiicant amount of interest recently, and many industry leaders, such as Google, Uber, Tesla and Mobileye, have invested large amount of capital and engineering power on developing such systems. Building autonomous driving systems is particularly challenging due to stringent performance requirements in terms of both making the safe operational decisions and inishing processing at real-time. Despite the recent advancements in technology, such systems are still largely under experimentation and architecting end-to-end autonomous driving systems remains an open research question. To investigate this question, we irst present and formalize the design constraints for building an autonomous driving system in terms of performance, predictability, storage, thermal and power. We then build an end-to-end autonomous driving system using state-of-the-art award-winning algorithms to understand the design trade-ofs for building such systems. In our real-system characterization, we identify three computational bottlenecks, which conventional multicore CPUs are incapable of processing under the identiied design constraints. To meet these constraints, we accelerate these algorithms using three accelerator platforms including GPUs, FPGAs and ASICs, which can reduce the tail latency of the system by 169×, 10×, and 93× respectively. With accelerator-based designs, we are able to build an endto-end autonomous driving system that meets all the design constraints, and explore the trade-ofs among performance, power and the higher accuracy enabled by higher resolution cameras. CCS Concepts • Computer systems organization → Neural networks; Heterogeneous (hybrid) systems;

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Section: Storage Constraintsmentioning

confidence: 99%

The Architectural Implications of Autonomous Driving

et al. 2018

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“…Liu et al [141] proposed the machine learning accelerator referred to as PuDianNao, that supports multiple machine learning scenarios (e.g., regression, classification, and clustering) as well as many machine learning techniques, including k-means, k-nearest neighbors, linear regression, classification tree, naive bayes, support vector machine, and DNNs. The PuDianNao mainly contains various Functional Units (FUs) and three types of data buffers: ColdBuf, HotBuf, and OutputBuf, an instruction buffer (InstBuf), and a DMA, and a control module, see Fig.…”

Section: A Alu Based Acceleratorsmentioning

confidence: 99%

“…The ShiDianNao accelerator is implemented using 65 nm CMOS technology. DianNao [53], DaDianNao [54], [146], PuDianNao [141], and ShiDianNao [78] are not built utilizing reconfigurable hardware, hence they cannot be adapted to changing application demands such as NN sizes.…”

Section: A Alu Based Acceleratorsmentioning

confidence: 99%

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

et al. 2022

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In the modern-day era of technology, a paradigm shift has been witnessed in the areas involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL). Specifically, Deep Neural Networks (DNNs) have emerged as a popular field of interest in most AI applications such as computer vision, image and video processing, robotics, etc. In the context of developed digital technologies and the availability of authentic data and data handling infrastructure, DNNs have been a credible choice for solving more complex real-life problems. The performance and accuracy of a DNN is a way better than human intelligence in certain situations. However, it is noteworthy that the DNN is computationally too cumbersome in terms of the resources and time to handle these computations. Furthermore, general-purpose architectures like CPUs have issues in handling such computationally intensive algorithms. Therefore, a lot of interest and efforts have been invested by the research fraternity in specialized hardware architectures such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), and Coarse Grained Reconfigurable Array (CGRA) in the context of effective implementation of computationally intensive algorithms. This paper brings forward the various research works on the development and deployment of DNNs using the aforementioned specialized hardware architectures and embedded AI accelerators. The review discusses the detailed description of the specialized hardware-based accelerators used in the training and/or inference of DNN. A comparative study based on factors like power, area, and throughput, is also made on the various accelerators discussed. Finally, future research and development directions, such as future trends in DNN implementation on specialized hardware accelerators, are discussed. This review article is intended to guide hardware architects to accelerate and improve the effectiveness of deep learning research.INDEX TERMS Machine learning, field programmable gate array (FPGA), deep neural networks (DNN), deep learning (DL), application specific integrated circuits (ASIC), artificial intelligence (AI), central processing unit (CPU), graphics processing unit (GPU), hardware accelerators. FIGURE 3. A single ANN neuron with its elements (inputs, weights, bias, summer, activation function, and output).

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“…In DianNao, the SPM is mainly categorized into two classes, that is, neuron buffer (including the input and output buffer, i.e., NBin and NBout) and SB. Other accelerators in DianNao family, including DaDianNao, 34 PuDianNao, 35 ShiDianNao, 36 and DianNao, 5 also employ the on‐chip SPM for efficiency. In addition to the DianNao family, other NN accelerators also leverage dedicated SPMs as precious resources for improving efficiency.…”

Section: Related Workmentioning

confidence: 99%

Space‐address decoupled scratchpad memory management for neural network accelerators

Zhang

Sun

Chen³

et al. 2020

Concurrency and Computation

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Deep neural networks have been demonstrated to be useful in varieties of intelligent tasks, and various specialized NN accelerators have been proposed recently to improve the hardware efficiency, which are typically equipped with software-managed scratchpad memory (SPM) for high performance and energy efficiency. However, traditional SPM management techniques cause memory fragmentation for NN accelerators, and thus lead to low utilization of precious SPM. The main reason is that traditional techniques are originally designed for managing fixed-length registers rather than variable-length memory blocks. In this article, we propose a novel SPM management approach for NN accelerators. The basic intuition is that NN computation/memory behaviors are predictable and relatively regular compared with traditional applications, and thus most information can be determined at compile time. In addition, by exploiting the variable-length feature of SPM, we propose to divide the allocation process into two passes: the space assignment and the address assignment pass, which are simultaneously (and implicitly) performed in traditional one-pass allocation techniques. Experimental results on the memory requests of a representative NN accelerator demonstrate that the proposed approach can significantly reduce the memory consumption by 30% at most compared with state-of-the-art SPM management techniques, and the memory usage is only 2% larger than that of the theoretical optimal allocation. K E Y W O R D S deep neural network, memory management, scratchpad memory 1 INTRODUCTION Deep neural networks (DNNs) have been widely used for various applications, such as computer vision, 1 speech recognition, 2 machine translation, 3 and robotics, 4 due to the improved accuracy over traditional machine learning approaches. However, the performance benefits of DNNs come at the cost of extremely high computation and memory complexity, which pose great challenges to underlying hardware architecture. To improve the efficiency of DNN processing, various specialized accelerators have been proposed to deliver orders of magnitude better performance and energy efficiency than general-purpose architectures such as CPUs and GPUs. 5,6 Specialized neural network accelerators typically require various novel architectural components, including control logics (e.g., DianNao 5 employs a control processor with dedicated control instructions and Eyeriss 6 employs two-level control hierarchy 6), computational units (e.g., DianNao employs 16-fix functional units to leverage the error-tolerance features of intelligent applications), and memory hierarchy Zhenxing Zhang and Shiyan Sun contributed equally to this work.

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PuDianNao

Cited by 168 publications

References 32 publications

The Architectural Implications of Autonomous Driving

The Architectural Implications of Autonomous Driving

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

Space‐address decoupled scratchpad memory management for neural network accelerators

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